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42 lines
1.3 KiB
Diff
42 lines
1.3 KiB
Diff
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From 3f40514a51b44171d274ef6a7d66dce9ae7c349d Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 24 May 2013 21:28:08 +0200
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Subject: [PATCH 17/33] USB: MIPS: ralink: fix usb issue on mt7620
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USB fails when frequency scaling is enabled. Increase the idle cpu speed when
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scaled.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/include/asm/mach-ralink/mt7620.h | 1 +
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arch/mips/ralink/mt7620.c | 8 ++++++++
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2 files changed, 9 insertions(+)
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--- a/arch/mips/include/asm/mach-ralink/mt7620.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
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@@ -20,6 +20,7 @@
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#define SYSC_REG_CHIP_REV 0x0c
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#define SYSC_REG_SYSTEM_CONFIG0 0x10
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#define SYSC_REG_SYSTEM_CONFIG1 0x14
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+#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
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#define SYSC_REG_CPLL_CONFIG0 0x54
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#define SYSC_REG_CPLL_CONFIG1 0x58
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -185,6 +185,14 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000500.uart", 40000000);
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ralink_clk_add("10000b00.spi", 40000000);
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ralink_clk_add("10000c00.uartlite", 40000000);
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+
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+#ifdef CONFIG_USB
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+ /*
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+ * When the CPU goes into sleep mode, the BUS clock will be too low for
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+ * USB to function properly
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+ */
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+ rt_sysc_m32(0x1f1f, 0x303, SYSC_REG_CPU_SYS_CLKCFG);
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+#endif
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}
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void __init ralink_of_remap(void)
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