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81 lines
2.3 KiB
Diff
81 lines
2.3 KiB
Diff
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From d8b6f5bae6d3b648a67b6958cb98e4e97256d652 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Thu, 14 Oct 2021 00:39:06 +0200
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Subject: dsa: qca8k: add mac_power_sel support
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Add missing mac power sel support needed for ipq8064/5 SoC that require
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1.8v for the internal regulator port instead of the default 1.5v.
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If other device needs this, consider adding a dedicated binding to
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support this.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 31 +++++++++++++++++++++++++++++++
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drivers/net/dsa/qca8k.h | 5 +++++
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2 files changed, 36 insertions(+)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -951,6 +951,33 @@ qca8k_setup_of_rgmii_delay(struct qca8k_
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}
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static int
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+qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
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+{
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+ u32 mask = 0;
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+ int ret = 0;
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+
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+ /* SoC specific settings for ipq8064.
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+ * If more device require this consider adding
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+ * a dedicated binding.
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+ */
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+ if (of_machine_is_compatible("qcom,ipq8064"))
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+ mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
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+
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+ /* SoC specific settings for ipq8065 */
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+ if (of_machine_is_compatible("qcom,ipq8065"))
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+ mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
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+
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+ if (mask) {
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+ ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
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+ QCA8K_MAC_PWR_RGMII0_1_8V |
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+ QCA8K_MAC_PWR_RGMII1_1_8V,
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+ mask);
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+ }
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+
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+ return ret;
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+}
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+
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+static int
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qca8k_setup(struct dsa_switch *ds)
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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@@ -979,6 +1006,10 @@ qca8k_setup(struct dsa_switch *ds)
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if (ret)
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return ret;
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+ ret = qca8k_setup_mac_pwr_sel(priv);
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+ if (ret)
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+ return ret;
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+
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/* Enable CPU Port */
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ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
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QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -100,6 +100,11 @@
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#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
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#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
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+/* MAC_PWR_SEL registers */
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+#define QCA8K_REG_MAC_PWR_SEL 0x0e4
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+#define QCA8K_MAC_PWR_RGMII1_1_8V BIT(18)
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+#define QCA8K_MAC_PWR_RGMII0_1_8V BIT(19)
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+
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/* EEE control registers */
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#define QCA8K_REG_EEE_CTRL 0x100
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#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
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