mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 10:08:59 +00:00
22 lines
668 B
Diff
22 lines
668 B
Diff
|
From 7d95f6b52ea5f01c9e2414d4984e5a274328c021 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Samuel Holland <samuel@sholland.org>
|
||
|
|
Date: Sun, 7 Aug 2022 10:58:57 -0500
|
||
|
|
Subject: [PATCH 093/117] riscv: dts: allwinner: d1: Add LVDS0 PHY
|
||
|
|
|
||
|
|
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
||
|
|
---
|
||
|
|
arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 2 ++
|
||
|
|
1 file changed, 2 insertions(+)
|
||
|
|
|
||
|
|
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
|
||
|
|
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
|
||
|
|
@@ -1040,6 +1040,8 @@
|
||
|
|
resets = <&ccu RST_BUS_TCON_LCD0>,
|
||
|
|
<&ccu RST_BUS_LVDS0>;
|
||
|
|
reset-names = "lcd", "lvds";
|
||
|
|
+ phys = <&dphy>;
|
||
|
|
+ phy-names = "lvds0";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
|
||
|
|
ports {
|