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48 lines
1.5 KiB
Diff
48 lines
1.5 KiB
Diff
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From d09357656ae3985095f562cf005fa94fd61ebfe6 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Tue, 1 Feb 2022 21:50:16 -0600
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Subject: [PATCH 038/117] crypto: sun8i-ce - Add TRNG clock to D1 variant
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At least the D1 variant requires a separate clock for the TRNG.
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Without this clock enabled, reading from /dev/hwrng reports:
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sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3
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Experimentation shows that the necessary clock is the SoC's internal
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RC oscillator. This makes sense, as the oscillator's frequency
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variations can be used as a source of randomness.
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Since D1 does not yet have a device tree, we can update this variant
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without breaking anything.
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Series-changes: 2
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- New patch
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 1 +
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drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 2 +-
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2 files changed, 2 insertions(+), 1 deletion(-)
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--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
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+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
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@@ -118,6 +118,7 @@ static const struct ce_variant ce_d1_var
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{ "bus", 0, 200000000 },
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{ "mod", 300000000, 0 },
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{ "ram", 0, 400000000 },
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+ { "trng", 0, 0 },
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},
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.esr = ESR_D1,
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.prng = CE_ALG_PRNG,
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--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
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+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
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@@ -105,7 +105,7 @@
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#define MAX_SG 8
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-#define CE_MAX_CLOCKS 3
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+#define CE_MAX_CLOCKS 4
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#define MAXFLOW 4
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