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openwrt/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch

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ipq40xx: add PSGMII PHY mode to phylink_get_linkmodes() Upstream commit ("net: phylink: add generic validate implementation") was backported, however PSGMII PHY mode patch for ipq40xx was not updated to add PSGMII to phylink_get_linkmodes() so the following warning would be printed during kernel compilation: drivers/net/phy/phylink.c: In function 'phylink_get_linkmodes': drivers/net/phy/phylink.c:360:9: error: enumeration value 'PHY_INTERFACE_MODE_PSGMII' not handled in switch [-Werror=switch] 360 | switch (interface) { | ^~~~~~ Resolve the warning by adding the PSGMII mode to phylink_get_linkmodes(). Signed-off-by: Robert Marko <robimarko@gmail.com>
2023-05-06 10:45:56 +00:00
From 157ac9f52fd9b9a22cf12f7755a905fb34ef72f7 Mon Sep 17 00:00:00 2001
ipq40xx: add PSGMII PHY mode define PSGMII is a Qualcomm specific mode similar to QSGMII but it has 5 SGMII lines instead of 4 in QSGMII. This just adds the support for the PHY layer to be able to identify the mode for further use. It is required for the DSA driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2021-11-01 12:02:53 +00:00
From: Gabor Juhos <j4g8y7@gmail.com>
Date: Fri, 25 Dec 2020 08:02:47 +0100
Subject: [PATCH] net: phy: define PSGMII PHY interface mode
The PSGMII interface is similar to QSGMII. The main difference
is that the PSGMII interface combines five SGMII lines into a
single link while in QSGMII only four lines are combined.
Similarly to the QSGMII, this interface mode might also needs
special handling within the MAC driver.
Add definitions for the PHY layer to allow to express this type
of connection between the MAC and PHY.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
ipq40xx: add PSGMII PHY mode to phylink_get_linkmodes() Upstream commit ("net: phylink: add generic validate implementation") was backported, however PSGMII PHY mode patch for ipq40xx was not updated to add PSGMII to phylink_get_linkmodes() so the following warning would be printed during kernel compilation: drivers/net/phy/phylink.c: In function 'phylink_get_linkmodes': drivers/net/phy/phylink.c:360:9: error: enumeration value 'PHY_INTERFACE_MODE_PSGMII' not handled in switch [-Werror=switch] 360 | switch (interface) { | ^~~~~~ Resolve the warning by adding the PSGMII mode to phylink_get_linkmodes(). Signed-off-by: Robert Marko <robimarko@gmail.com>
2023-05-06 10:45:56 +00:00
drivers/net/phy/phylink.c | 2 ++
ipq40xx: add PSGMII PHY mode define PSGMII is a Qualcomm specific mode similar to QSGMII but it has 5 SGMII lines instead of 4 in QSGMII. This just adds the support for the PHY layer to be able to identify the mode for further use. It is required for the DSA driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2021-11-01 12:02:53 +00:00
include/linux/phy.h | 3 +++
ipq40xx: add PSGMII PHY mode to phylink_get_linkmodes() Upstream commit ("net: phylink: add generic validate implementation") was backported, however PSGMII PHY mode patch for ipq40xx was not updated to add PSGMII to phylink_get_linkmodes() so the following warning would be printed during kernel compilation: drivers/net/phy/phylink.c: In function 'phylink_get_linkmodes': drivers/net/phy/phylink.c:360:9: error: enumeration value 'PHY_INTERFACE_MODE_PSGMII' not handled in switch [-Werror=switch] 360 | switch (interface) { | ^~~~~~ Resolve the warning by adding the PSGMII mode to phylink_get_linkmodes(). Signed-off-by: Robert Marko <robimarko@gmail.com>
2023-05-06 10:45:56 +00:00
3 files changed, 6 insertions(+)
ipq40xx: add PSGMII PHY mode define PSGMII is a Qualcomm specific mode similar to QSGMII but it has 5 SGMII lines instead of 4 in QSGMII. This just adds the support for the PHY layer to be able to identify the mode for further use. It is required for the DSA driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2021-11-01 12:02:53 +00:00
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -64,6 +64,7 @@ properties:
- mii
- gmii
- sgmii
+ - psgmii
- qsgmii
- tbi
- rev-mii
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
ipq40xx: add PSGMII PHY mode to phylink_get_linkmodes() Upstream commit ("net: phylink: add generic validate implementation") was backported, however PSGMII PHY mode patch for ipq40xx was not updated to add PSGMII to phylink_get_linkmodes() so the following warning would be printed during kernel compilation: drivers/net/phy/phylink.c: In function 'phylink_get_linkmodes': drivers/net/phy/phylink.c:360:9: error: enumeration value 'PHY_INTERFACE_MODE_PSGMII' not handled in switch [-Werror=switch] 360 | switch (interface) { | ^~~~~~ Resolve the warning by adding the PSGMII mode to phylink_get_linkmodes(). Signed-off-by: Robert Marko <robimarko@gmail.com>
2023-05-06 10:45:56 +00:00
@@ -366,6 +366,7 @@ void phylink_get_linkmodes(unsigned long
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_PSGMII:
case PHY_INTERFACE_MODE_QSGMII:
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_GMII:
@@ -629,6 +630,7 @@ static int phylink_parse_mode(struct phy
ipq40xx: add PSGMII PHY mode define PSGMII is a Qualcomm specific mode similar to QSGMII but it has 5 SGMII lines instead of 4 in QSGMII. This just adds the support for the PHY layer to be able to identify the mode for further use. It is required for the DSA driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2021-11-01 12:02:53 +00:00
switch (pl->link_config.interface) {
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_PSGMII:
case PHY_INTERFACE_MODE_QSGMII:
phylink_set(pl->supported, 10baseT_Half);
phylink_set(pl->supported, 10baseT_Full);
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -138,6 +138,7 @@ typedef enum {
PHY_INTERFACE_MODE_XGMII,
PHY_INTERFACE_MODE_XLGMII,
PHY_INTERFACE_MODE_MOCA,
+ PHY_INTERFACE_MODE_PSGMII,
PHY_INTERFACE_MODE_QSGMII,
PHY_INTERFACE_MODE_TRGMII,
PHY_INTERFACE_MODE_100BASEX,
kernel: bump 5.15 to 5.15.72 Removed upstreamed: generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch[1] bcm53xx/patches-5.15/082-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch[2] All other patches automatically rebased Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200, mvebu/cortexa72 Run-tested: bcm2711/RPi4B, mt7622/RT3200, mvebu/cortexa72 (RB5009UG+S+IN) 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.72&id=5de02ab84aeca765da0e4d8e999af35325ac67c2 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.72&id=ab5c5787ab5ecdc4a7ea20b4ef542579e1beb49d Signed-off-by: John Audia <therealgraysky@proton.me>
2022-10-05 10:04:11 +00:00
@@ -243,6 +244,8 @@ static inline const char *phy_modes(phy_
ipq40xx: add PSGMII PHY mode define PSGMII is a Qualcomm specific mode similar to QSGMII but it has 5 SGMII lines instead of 4 in QSGMII. This just adds the support for the PHY layer to be able to identify the mode for further use. It is required for the DSA driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2021-11-01 12:02:53 +00:00
return "xlgmii";
case PHY_INTERFACE_MODE_MOCA:
return "moca";
+ case PHY_INTERFACE_MODE_PSGMII:
+ return "psgmii";
case PHY_INTERFACE_MODE_QSGMII:
return "qsgmii";
case PHY_INTERFACE_MODE_TRGMII:
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