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62 lines
2.0 KiB
Diff
62 lines
2.0 KiB
Diff
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From dda83b1fb650670b865e8735115c00bdfccacabf Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Fri, 24 May 2024 14:49:28 +0100
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Subject: [PATCH 1107/1135] DTS: overlays: add mmio-hi parameter to
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pciex1-compat-pi5
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I225-V network adapters have a buggy ROM that won't complete internal
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initialisation if (at least) BAR0 has an assigned address of 0x0.
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Add a parameter to the pciex1-compat-pi5 overlay to make outbound
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addresses start at 2GB.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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arch/arm/boot/dts/overlays/README | 2 ++
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.../overlays/pciex1-compat-pi5-overlay.dts | 20 +++++++++++++++++++
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2 files changed, 22 insertions(+)
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--- a/arch/arm/boot/dts/overlays/README
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+++ b/arch/arm/boot/dts/overlays/README
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@@ -3550,6 +3550,8 @@ Params: l1ss Enable A
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the MSI-MIP peripheral. Use if a) more than 8
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interrupt vectors are required or b) the EP
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requires DMA and MSI addresses to be 32bit.
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+ mmio-hi Move the start of outbound 32bit addresses to
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+ 2GB and expand 64bit outbound space to 14GB.
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[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]
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--- a/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
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+++ b/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
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@@ -32,9 +32,29 @@
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};
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};
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+ /*
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+ * Shift the start of the 32bit outbound window to 2GB,
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+ * so there are no BARs starting at 0x0. Expand the 64bit
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+ * outbound window to use the spare 2GB.
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+ */
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+ fragment@3 {
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+ target = <&pciex1>;
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+ __dormant__ {
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ ranges = <0x02000000 0x00 0x80000000
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+ 0x1b 0x80000000
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+ 0x00 0x7ffffffc>,
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+ <0x43000000 0x04 0x00000000
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+ 0x18 0x00000000
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+ 0x03 0x80000000>;
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+ };
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+ };
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+
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__overrides__ {
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l1ss = <0>, "+0";
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no-l0s = <0>, "+1";
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no-mip = <0>, "+2";
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+ mmio-hi = <0>, "+3";
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};
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};
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