2022-08-31 12:31:02 +00:00
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From d19ad7515a7ef4ee58b5c6606ee9f74c94f28932 Mon Sep 17 00:00:00 2001
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2022-07-12 02:41:30 +00:00
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From: Weijie Gao <weijie.gao@mediatek.com>
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2022-08-31 12:31:02 +00:00
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Date: Wed, 31 Aug 2022 19:04:32 +0800
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Subject: [PATCH 10/32] serial: mtk: add support for using dynamic baud clock
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2022-07-12 02:41:30 +00:00
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souce
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The baud clock on some platform may change due to assigned-clock-parent
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set in DT. In current flow the baud clock is only retrieved during probe
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stage. If the parent of the source clock changes after probe stage, the
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setbrg will set wrong baudrate.
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To get the right clock rate, this patch records the baud clk struct to the
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driver's priv, and changes the driver's flow to get the clock rate before
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calling _mtk_serial_setbrg().
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Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/serial/serial_mtk.c | 80 ++++++++++++++++++++++---------------
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1 file changed, 47 insertions(+), 33 deletions(-)
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--- a/drivers/serial/serial_mtk.c
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+++ b/drivers/serial/serial_mtk.c
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@@ -10,6 +10,7 @@
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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+#include <dm/device_compat.h>
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#include <errno.h>
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#include <log.h>
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#include <serial.h>
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@@ -70,27 +71,37 @@ struct mtk_serial_regs {
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#define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
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#define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
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+/* struct mtk_serial_priv - Structure holding all information used by the
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+ * driver
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+ * @regs: Register base of the serial port
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+ * @clk: The baud clock device
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+ * @fixed_clk_rate: Fallback fixed baud clock rate if baud clock
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+ * device is not specified
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+ * @force_highspeed: Force using high-speed mode
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+ */
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struct mtk_serial_priv {
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struct mtk_serial_regs __iomem *regs;
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- u32 clock;
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+ struct clk clk;
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+ u32 fixed_clk_rate;
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bool force_highspeed;
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};
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-static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
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+static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud,
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+ uint clk_rate)
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{
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u32 quot, realbaud, samplecount = 1;
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/* Special case for low baud clock */
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- if (baud <= 115200 && priv->clock <= 12000000) {
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+ if (baud <= 115200 && clk_rate == 12000000) {
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writel(3, &priv->regs->highspeed);
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- quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
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+ quot = DIV_ROUND_CLOSEST(clk_rate, 256 * baud);
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if (quot == 0)
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quot = 1;
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- samplecount = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
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+ samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud);
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- realbaud = priv->clock / samplecount / quot;
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+ realbaud = clk_rate / samplecount / quot;
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if (realbaud > BAUD_ALLOW_MAX(baud) ||
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realbaud < BAUD_ALLOW_MIX(baud)) {
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pr_info("baud %d can't be handled\n", baud);
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@@ -104,7 +115,7 @@ static void _mtk_serial_setbrg(struct mt
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if (baud <= 115200) {
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writel(0, &priv->regs->highspeed);
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- quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);
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+ quot = DIV_ROUND_CLOSEST(clk_rate, 16 * baud);
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} else if (baud <= 576000) {
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writel(2, &priv->regs->highspeed);
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@@ -112,13 +123,13 @@ static void _mtk_serial_setbrg(struct mt
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if ((baud == 500000) || (baud == 576000))
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baud = 460800;
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- quot = DIV_ROUND_UP(priv->clock, 4 * baud);
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+ quot = DIV_ROUND_UP(clk_rate, 4 * baud);
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} else {
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use_hs3:
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writel(3, &priv->regs->highspeed);
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- quot = DIV_ROUND_UP(priv->clock, 256 * baud);
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- samplecount = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
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+ quot = DIV_ROUND_UP(clk_rate, 256 * baud);
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+ samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud);
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}
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set_baud:
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@@ -167,8 +178,13 @@ static int _mtk_serial_pending(struct mt
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static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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+ u32 clk_rate;
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+
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+ clk_rate = clk_get_rate(&priv->clk);
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+ if (IS_ERR_VALUE(clk_rate) || clk_rate == 0)
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+ clk_rate = priv->fixed_clk_rate;
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- _mtk_serial_setbrg(priv, baudrate);
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+ _mtk_serial_setbrg(priv, baudrate, clk_rate);
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return 0;
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}
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@@ -211,7 +227,6 @@ static int mtk_serial_of_to_plat(struct
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{
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struct mtk_serial_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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- struct clk clk;
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int err;
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addr = dev_read_addr(dev);
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@@ -220,22 +235,19 @@ static int mtk_serial_of_to_plat(struct
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priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
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- err = clk_get_by_index(dev, 0, &clk);
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- if (!err) {
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- err = clk_get_rate(&clk);
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- if (!IS_ERR_VALUE(err))
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- priv->clock = err;
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- } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
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- debug("mtk_serial: failed to get clock\n");
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- return err;
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- }
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-
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- if (!priv->clock)
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- priv->clock = dev_read_u32_default(dev, "clock-frequency", 0);
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-
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- if (!priv->clock) {
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- debug("mtk_serial: clock not defined\n");
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- return -EINVAL;
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+ err = clk_get_by_index(dev, 0, &priv->clk);
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+ if (err) {
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+ err = dev_read_u32(dev, "clock-frequency", &priv->fixed_clk_rate);
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+ if (err) {
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+ dev_err(dev, "baud clock not defined\n");
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+ return -EINVAL;
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+ }
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+ } else {
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+ err = clk_get_rate(&priv->clk);
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+ if (IS_ERR_VALUE(err)) {
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+ dev_err(dev, "invalid baud clock\n");
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+ return -EINVAL;
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+ }
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}
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priv->force_highspeed = dev_read_bool(dev, "mediatek,force-highspeed");
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@@ -273,7 +285,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define DECLARE_HSUART_PRIV(port) \
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static struct mtk_serial_priv mtk_hsuart##port = { \
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.regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
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- .clock = CONFIG_SYS_NS16550_CLK \
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+ .fixed_clk_rate = CONFIG_SYS_NS16550_CLK \
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};
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#define DECLARE_HSUART_FUNCTIONS(port) \
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@@ -282,12 +294,14 @@ DECLARE_GLOBAL_DATA_PTR;
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writel(0, &mtk_hsuart##port.regs->ier); \
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writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
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writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
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- _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
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+ _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate, \
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+ mtk_hsuart##port.fixed_clk_rate); \
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return 0 ; \
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} \
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static void mtk_serial##port##_setbrg(void) \
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{ \
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- _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
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+ _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate, \
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+ mtk_hsuart##port.fixed_clk_rate); \
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} \
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static int mtk_serial##port##_getc(void) \
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{ \
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@@ -427,13 +441,13 @@ static inline void _debug_uart_init(void
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struct mtk_serial_priv priv;
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2022-08-31 12:31:02 +00:00
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priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
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2022-07-12 02:41:30 +00:00
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- priv.clock = CONFIG_DEBUG_UART_CLOCK;
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+ priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK;
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writel(0, &priv.regs->ier);
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writel(UART_MCRVAL, &priv.regs->mcr);
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writel(UART_FCRVAL, &priv.regs->fcr);
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- _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
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+ _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE, priv.fixed_clk_rate);
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}
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static inline void _debug_uart_putc(int ch)
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