openwrt/target/linux/starfive/patches-6.1/1008-dmaengine-dw-axi-dmac-Add-StarFive-JH7100-support.patch

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From c06352c09ce55999d41036e593293a3aaf0cf70c Mon Sep 17 00:00:00 2001
From: Samin Guo <samin.guo@starfivetech.com>
Date: Wed, 17 Nov 2021 14:50:45 +0800
Subject: [PATCH 1008/1024] dmaengine: dw-axi-dmac: Add StarFive JH7100 support
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 12 ++++++++++++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 4 ++++
2 files changed, 16 insertions(+)
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -677,8 +677,13 @@ static int dw_axi_dma_set_hw_desc(struct
hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
+#ifdef CONFIG_SOC_STARFIVE
+ ctllo |= DWAXIDMAC_BURST_TRANS_LEN_16 << CH_CTL_L_DST_MSIZE_POS |
+ DWAXIDMAC_BURST_TRANS_LEN_16 << CH_CTL_L_SRC_MSIZE_POS;
+#else
ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
+#endif
hw_desc->lli->ctl_lo = cpu_to_le32(ctllo);
set_desc_src_master(hw_desc);
@@ -1508,7 +1513,11 @@ static int dw_probe(struct platform_devi
* Therefore, set constraint to 1024 * 4.
*/
dw->dma.dev->dma_parms = &dw->dma_parms;
+#ifdef CONFIG_SOC_STARFIVE
+ dma_set_max_seg_size(&pdev->dev, DMAC_MAX_BLK_SIZE);
+#else
dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
+#endif
platform_set_drvdata(pdev, chip);
pm_runtime_enable(chip->dev);
@@ -1593,6 +1602,9 @@ static const struct of_device_id dw_dma_
.compatible = "intel,kmb-axi-dma",
.data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
}, {
+ .compatible = "starfive,jh7100-axi-dma",
+ .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
+ }, {
.compatible = "starfive,jh7110-axi-dma",
.data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
},
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -283,7 +283,11 @@ enum {
#define CH_CTL_L_SRC_MAST BIT(0)
/* CH_CFG_H */
+#ifdef CONFIG_SOC_STARFIVE
+#define CH_CFG_H_PRIORITY_POS 15
+#else
#define CH_CFG_H_PRIORITY_POS 17
+#endif
#define CH_CFG_H_DST_PER_POS 12
#define CH_CFG_H_SRC_PER_POS 7
#define CH_CFG_H_HS_SEL_DST_POS 4