mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
33 lines
1.0 KiB
Diff
33 lines
1.0 KiB
Diff
|
From 6a9196186f9630006c3db022bcc0bd5796f4fae5 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Emil Renner Berthing <kernel@esmil.dk>
|
||
|
|
Date: Sat, 20 Nov 2021 17:13:22 +0100
|
||
|
|
Subject: [PATCH 1004/1024] RISC-V: Add StarFive JH7100 audio clock node
|
||
|
|
|
||
|
|
Add device tree node for the audio clocks on the StarFive JH7100 RISC-V
|
||
|
|
SoC.
|
||
|
|
|
||
|
|
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
|
||
|
|
---
|
||
|
|
arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++
|
||
|
|
1 file changed, 10 insertions(+)
|
||
|
|
|
||
|
|
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
||
|
|
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
||
|
|
@@ -133,6 +133,16 @@
|
||
|
|
riscv,ndev = <133>;
|
||
|
|
};
|
||
|
|
|
||
|
|
+ audclk: clock-controller@10480000 {
|
||
|
|
+ compatible = "starfive,jh7100-audclk";
|
||
|
|
+ reg = <0x0 0x10480000 0x0 0x10000>;
|
||
|
|
+ clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
|
||
|
|
+ <&clkgen JH7100_CLK_AUDIO_12288>,
|
||
|
|
+ <&clkgen JH7100_CLK_DOM7AHB_BUS>;
|
||
|
|
+ clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
|
||
|
|
+ #clock-cells = <1>;
|
||
|
|
+ };
|
||
|
|
+
|
||
|
|
clkgen: clock-controller@11800000 {
|
||
|
|
compatible = "starfive,jh7100-clkgen";
|
||
|
|
reg = <0x0 0x11800000 0x0 0x10000>;
|