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69 lines
2.5 KiB
Diff
69 lines
2.5 KiB
Diff
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From 61d4a1751cfe5a22e5f18478fe16ffb1ee12607d Mon Sep 17 00:00:00 2001
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Date: Tue, 5 Apr 2022 08:34:44 +0200
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Subject: [PATCH] arm64: dts: qcom: align clocks in I2C/SPI with DT schema
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The DT schema expects clocks core-iface order. No functional change.
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Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++++++++------------
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1 file changed, 12 insertions(+), 12 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -467,9 +467,9 @@
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#size-cells = <0>;
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reg = <0x078b6000 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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- clock-names = "iface", "core";
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+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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clock-frequency = <400000>;
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dmas = <&blsp_dma 14>, <&blsp_dma 15>;
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dma-names = "tx", "rx";
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@@ -484,9 +484,9 @@
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#size-cells = <0>;
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reg = <0x078b7000 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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- clock-names = "iface", "core";
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+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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clock-frequency = <100000>;
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dmas = <&blsp_dma 16>, <&blsp_dma 17>;
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dma-names = "tx", "rx";
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@@ -499,9 +499,9 @@
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#size-cells = <0>;
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reg = <0x78b9000 0x600>;
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interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
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- clock-names = "iface", "core";
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+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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clock-frequency = <400000>;
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dmas = <&blsp_dma 20>, <&blsp_dma 21>;
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dma-names = "tx", "rx";
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@@ -514,9 +514,9 @@
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#size-cells = <0>;
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reg = <0x078ba000 0x600>;
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interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
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- clock-names = "iface", "core";
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+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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clock-frequency = <100000>;
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dmas = <&blsp_dma 22>, <&blsp_dma 23>;
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dma-names = "tx", "rx";
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