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74 lines
3.1 KiB
Diff
74 lines
3.1 KiB
Diff
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From 4a1990ee249df257848f9583cef71478e3411c3e Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Thu, 28 Dec 2017 11:24:45 +0800
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Subject: [PATCH 201/224] dt-bindings: clock: mediatek: add missing required
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#reset-cells
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All ethsys, pciesys and ssusbsys internally include reset controller, so
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explicitly add back these missing cell definitions to related bindings
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and examples.
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Cc: Rob Herring <robh@kernel.org>
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Cc: Michael Turquette <mturquette@baylibre.com>
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Cc: Stephen Boyd <sboyd@codeaurora.org>
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Cc: linux-clk@vger.kernel.org
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Reviewed-by: Rob Herring <robh@kernel.org>
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---
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Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
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Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++
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Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++
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3 files changed, 5 insertions(+)
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diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
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index 7aa3fa167668..52757adf86bb 100644
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
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@@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2701-ethsys", "syscon"
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- "mediatek,mt7622-ethsys", "syscon"
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- #clock-cells: Must be 1
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+- #reset-cells: Must be 1
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The ethsys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
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index d5d5f1227665..7fe5dc6097a6 100644
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt7622-pciesys", "syscon"
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- #clock-cells: Must be 1
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+- #reset-cells: Must be 1
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The PCIESYS controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
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compatible = "mediatek,mt7622-pciesys", "syscon";
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reg = <0 0x1a100800 0 0x1000>;
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#clock-cells = <1>;
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+ #reset-cells = <1>;
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};
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diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
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index 00760019da00..b8184da2508c 100644
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt7622-ssusbsys", "syscon"
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- #clock-cells: Must be 1
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+- #reset-cells: Must be 1
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The SSUSBSYS controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
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compatible = "mediatek,mt7622-ssusbsys", "syscon";
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reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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+ #reset-cells = <1>;
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};
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--
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2.11.0
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