2023-09-14 10:44:02 +00:00
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From 492b06747f544c19b5ffe531a24b67858764c50e Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
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Date: Mon, 29 May 2023 10:02:44 +0200
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Subject: [PATCH 896/898] net: dsa: mv88e6xxx: fix 88E6393X family internal
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phys layout
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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88E6393X/88E6193X/88E6191X switches have in fact 8 internal PHYs, but those
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are not present starting at port 0: supported ports go from 1 to 8
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Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/dsa/mv88e6xxx/chip.c | 9 ++++++---
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1 file changed, 6 insertions(+), 3 deletions(-)
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--- a/drivers/net/dsa/mv88e6xxx/chip.c
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+++ b/drivers/net/dsa/mv88e6xxx/chip.c
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2024-06-29 14:38:42 +00:00
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@@ -5414,7 +5414,8 @@ static const struct mv88e6xxx_info mv88e
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2023-09-14 10:44:02 +00:00
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.name = "Marvell 88E6191X",
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.num_databases = 4096,
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.num_ports = 11, /* 10 + Z80 */
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- .num_internal_phys = 9,
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+ .num_internal_phys = 8,
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+ .internal_phys_offset = 1,
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.max_vid = 8191,
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.port_base_addr = 0x0,
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.phy_base_addr = 0x0,
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2024-06-29 14:38:42 +00:00
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@@ -5436,7 +5437,8 @@ static const struct mv88e6xxx_info mv88e
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2023-09-14 10:44:02 +00:00
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.name = "Marvell 88E6193X",
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.num_databases = 4096,
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.num_ports = 11, /* 10 + Z80 */
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- .num_internal_phys = 9,
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+ .num_internal_phys = 8,
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+ .internal_phys_offset = 1,
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.max_vid = 8191,
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.port_base_addr = 0x0,
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.phy_base_addr = 0x0,
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2024-06-29 14:38:42 +00:00
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@@ -5746,7 +5748,8 @@ static const struct mv88e6xxx_info mv88e
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2023-09-14 10:44:02 +00:00
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.name = "Marvell 88E6393X",
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.num_databases = 4096,
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.num_ports = 11, /* 10 + Z80 */
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- .num_internal_phys = 9,
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+ .num_internal_phys = 8,
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+ .internal_phys_offset = 1,
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.max_vid = 8191,
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.port_base_addr = 0x0,
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.phy_base_addr = 0x0,
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