2021-11-04 20:52:43 +00:00
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From 3b00a07c2443745d62babfe08dbb2ad8e649526e Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Fri, 19 Nov 2021 03:03:49 +0100
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Subject: [PATCH] net: dsa: qca8k: fix internal delay applied to the wrong PAD
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config
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With SGMII phy the internal delay is always applied to the PAD0 config.
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This is caused by the falling edge configuration that hardcode the reg
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to PAD0 (as the falling edge bits are present only in PAD0 reg)
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Move the delay configuration before the reg overwrite to correctly apply
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the delay.
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Fixes: cef08115846e ("net: dsa: qca8k: set internal delay also for sgmii")
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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2022-03-21 14:21:24 +00:00
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@@ -1433,6 +1433,12 @@ qca8k_phylink_mac_config(struct dsa_swit
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2021-11-04 20:52:43 +00:00
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qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
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+ /* From original code is reported port instability as SGMII also
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+ * require delay set. Apply advised values here or take them from DT.
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+ */
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+ if (state->interface == PHY_INTERFACE_MODE_SGMII)
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+ qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
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+
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/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
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* falling edge is set writing in the PORT0 PAD reg
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*/
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2022-03-21 14:21:24 +00:00
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@@ -1455,12 +1461,6 @@ qca8k_phylink_mac_config(struct dsa_swit
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2021-11-04 20:52:43 +00:00
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QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
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val);
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- /* From original code is reported port instability as SGMII also
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- * require delay set. Apply advised values here or take them from DT.
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- */
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- if (state->interface == PHY_INTERFACE_MODE_SGMII)
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- qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
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-
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break;
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default:
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dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
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