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49 lines
2.0 KiB
Diff
49 lines
2.0 KiB
Diff
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commit 1dde977518f13824b847e23275001191139bc384
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Author: Alexandre Ghiti <alexandre.ghiti@canonical.com>
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Date: Mon Oct 3 18:07:54 2022 +0200
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riscv: Fix build against binutils 2.38
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The following description is copied from the equivalent patch for the
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Linux Kernel proposed by Aurelien Jarno:
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>From version 2.38, binutils default to ISA spec version 20191213. This
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means that the csr read/write (csrr*/csrw*) instructions and fence.i
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instruction has separated from the `I` extension, become two standalone
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extensions: Zicsr and Zifencei. As the kernel uses those instruction,
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this causes the following build failure:
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arch/riscv/cpu/mtrap.S: Assembler messages:
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arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
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arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
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arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
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arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
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Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
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Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Tested-by: Heiko Stuebner <heiko@sntech.de>
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Tested-by: Christian Stewart <christian@paral.in>
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Reviewed-by: Rick Chen <rick@andestech.com>
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--- a/arch/riscv/Makefile
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+++ b/arch/riscv/Makefile
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@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
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CMODEL = medany
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endif
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-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
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+RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
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+
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+# Newer binutils versions default to ISA spec version 20191213 which moves some
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+# instructions from the I extension to the Zicsr and Zifencei extensions.
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+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
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+ifeq ($(toolchain-need-zicsr-zifencei),y)
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+ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
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+endif
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+
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+ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
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-mcmodel=$(CMODEL)
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PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
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