openwrt/package/boot/arm-trusted-firmware-stm32/patches/0001-Revert-feat-stm32mp1-fdts-remove-RTC-clock-configura.patch

From 0e1a71d84585ec33b479c2cb8c8d65a4f6734dbe Mon Sep 17 00:00:00 2001
From: Thomas Richard <thomas.richard@bootlin.com>
Date: Wed, 4 Dec 2024 14:26:52 +0100
Subject: [PATCH] Revert "feat(stm32mp1-fdts): remove RTC clock configuration"

This reverts commit 703a581e2522bffe21b421c98994dc02aed2934c.
---
 fdts/stm32mp135f-dk.dts   | 2 ++
 fdts/stm32mp157c-ed1.dts  | 2 ++
 fdts/stm32mp15xx-dkx.dtsi | 2 ++
 3 files changed, 6 insertions(+)

--- a/fdts/stm32mp135f-dk.dts
+++ b/fdts/stm32mp135f-dk.dts
@@ -190,6 +190,7 @@
 		CLK_AXI_PLL2P
 		CLK_MLAHBS_PLL3
 		CLK_CKPER_HSE
+		CLK_RTC_LSE
 		CLK_SDMMC1_PLL4P
 		CLK_SDMMC2_PLL4P
 		CLK_STGEN_HSE
@@ -211,6 +212,7 @@
 		DIV(DIV_APB4, 1)
 		DIV(DIV_APB5, 2)
 		DIV(DIV_APB6, 1)
+		DIV(DIV_RTC, 0)
 	>;
 
 	st,pll_vco {
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -194,6 +194,7 @@
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P
 		CLK_MCU_PLL3P
+		CLK_RTC_LSE
 		CLK_MCO1_DISABLED
 		CLK_MCO2_DISABLED
 		CLK_CKPER_HSE
@@ -242,6 +243,7 @@
 		DIV(DIV_APB3, 1)
 		DIV(DIV_APB4, 1)
 		DIV(DIV_APB5, 2)
+		DIV(DIV_RTC, 23)
 		DIV(DIV_MCO1, 0)
 		DIV(DIV_MCO2, 0)
 	>;
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -198,6 +198,7 @@
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P
 		CLK_MCU_PLL3P
+		CLK_RTC_LSE
 		CLK_MCO1_DISABLED
 		CLK_MCO2_DISABLED
 		CLK_CKPER_HSE
@@ -246,6 +247,7 @@
 		DIV(DIV_APB3, 1)
 		DIV(DIV_APB4, 1)
 		DIV(DIV_APB5, 2)
+		DIV(DIV_RTC, 23)
 		DIV(DIV_MCO1, 0)
 		DIV(DIV_MCO2, 0)
 	>;
arm-trusted-firmware-stm32: bump to v2.12 No need to pass the option no-warn-rwx-segments. Since v2.12, TF-A automatically selects it if needed. A patch is added to revert commit 03a581e2 ("feat(stm32mp1-fdts): remove RTC clock configuration"). This commit removed RTC clock configuration, as it assumed that it was done correctly by OPTEE. But it is not the case. Without this patch the RTC is in a bad state, consequently the wifi module cannot be initialized. stm32_rtc 5c004000.rtc: rtc_ck is slow stm32_rtc 5c004000.rtc: Can't enter in init mode. Prescaler config failed. stm32_rtc: probe of 5c004000.rtc failed with error -110 sdio mmc1:0001:1: Direct firmware load for brcm/brcmfmac43430-sdio.st,stm32mp135f-dk.bin failed with error -2 brcmfmac: brcmf_sdio_htclk: HT Avail timeout (1000000): clkctl 0x50 Tested on STM32MP135F-DK. Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Link: https://github.com/openwrt/openwrt/pull/17243 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> 2024-11-29 10:53:14 +00:00			`From 0e1a71d84585ec33b479c2cb8c8d65a4f6734dbe Mon Sep 17 00:00:00 2001`
			`From: Thomas Richard <thomas.richard@bootlin.com>`
			`Date: Wed, 4 Dec 2024 14:26:52 +0100`
			`Subject: [PATCH] Revert "feat(stm32mp1-fdts): remove RTC clock configuration"`

			`This reverts commit 703a581e2522bffe21b421c98994dc02aed2934c.`
			`---`
			`fdts/stm32mp135f-dk.dts \| 2 ++`
			`fdts/stm32mp157c-ed1.dts \| 2 ++`
			`fdts/stm32mp15xx-dkx.dtsi \| 2 ++`
			`3 files changed, 6 insertions(+)`

			`--- a/fdts/stm32mp135f-dk.dts`
			`+++ b/fdts/stm32mp135f-dk.dts`
			`@@ -190,6 +190,7 @@`
			`CLK_AXI_PLL2P`
			`CLK_MLAHBS_PLL3`
			`CLK_CKPER_HSE`
			`+ CLK_RTC_LSE`
			`CLK_SDMMC1_PLL4P`
			`CLK_SDMMC2_PLL4P`
			`CLK_STGEN_HSE`
			`@@ -211,6 +212,7 @@`
			`DIV(DIV_APB4, 1)`
			`DIV(DIV_APB5, 2)`
			`DIV(DIV_APB6, 1)`
			`+ DIV(DIV_RTC, 0)`
			`>;`

			`st,pll_vco {`
			`--- a/fdts/stm32mp157c-ed1.dts`
			`+++ b/fdts/stm32mp157c-ed1.dts`
			`@@ -194,6 +194,7 @@`
			`CLK_MPU_PLL1P`
			`CLK_AXI_PLL2P`
			`CLK_MCU_PLL3P`
			`+ CLK_RTC_LSE`
			`CLK_MCO1_DISABLED`
			`CLK_MCO2_DISABLED`
			`CLK_CKPER_HSE`
			`@@ -242,6 +243,7 @@`
			`DIV(DIV_APB3, 1)`
			`DIV(DIV_APB4, 1)`
			`DIV(DIV_APB5, 2)`
			`+ DIV(DIV_RTC, 23)`
			`DIV(DIV_MCO1, 0)`
			`DIV(DIV_MCO2, 0)`
			`>;`
			`--- a/fdts/stm32mp15xx-dkx.dtsi`
			`+++ b/fdts/stm32mp15xx-dkx.dtsi`
			`@@ -198,6 +198,7 @@`
			`CLK_MPU_PLL1P`
			`CLK_AXI_PLL2P`
			`CLK_MCU_PLL3P`
			`+ CLK_RTC_LSE`
			`CLK_MCO1_DISABLED`
			`CLK_MCO2_DISABLED`
			`CLK_CKPER_HSE`
			`@@ -246,6 +247,7 @@`
			`DIV(DIV_APB3, 1)`
			`DIV(DIV_APB4, 1)`
			`DIV(DIV_APB5, 2)`
			`+ DIV(DIV_RTC, 23)`
			`DIV(DIV_MCO1, 0)`
			`DIV(DIV_MCO2, 0)`
			`>;`