kernel: 5.4: import wireguard backport
Rather than using the clunky, old, slower wireguard-linux-compat out of
tree module, this commit does a patch-by-patch backport of upstream's
wireguard to 5.4. This specific backport is in widespread use, being
part of SUSE's enterprise kernel, Oracle's enterprise kernel, Google's
Android kernel, Gentoo's distro kernel, and probably more I've forgotten
about. It's definately the "more proper" way of adding wireguard to a
kernel than the ugly compat.h hell of the wireguard-linux-compat repo.
And most importantly for OpenWRT, it allows using the same module
configuration code for 5.10 as for 5.4, with no need for bifurcation.
These patches are from the backport tree which is maintained in the
open here: https://git.zx2c4.com/wireguard-linux/log/?h=backport-5.4.y
I'll be sending PRs to update this as needed.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
(cherry picked from commit 3888fa78802354ab7bbd19b7d061fd80a16ce06b)
(cherry picked from commit d54072587146dd0db9bb52b513234d944edabda3)
(cherry picked from commit 196f3d586f11d96ba4ab60068cfb12420bcd20fd)
(cherry picked from commit 3500fd7938a6d0c0e320295f0aa2fa34b1ebc08d)
(cherry picked from commit 23b801d3ba57e34cc609ea40982c7fbed08164e9)
(cherry picked from commit 0c0cb97da7f5cc06919449131dd57ed805f8f78d)
(cherry picked from commit 2a27f6f90a430342cdbe84806e8b10acff446a2d)
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
2021-02-19 13:29:04 +00:00
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From 31ca877744d95713e4925de542e1c686ab08a542 Mon Sep 17 00:00:00 2001
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From: "Jason A. Donenfeld" <Jason@zx2c4.com>
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Date: Sat, 27 Feb 2021 13:20:24 +0100
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Subject: [PATCH] MIPS: select CPU_MIPS64 for remaining MIPS64 CPUs
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The CPU_MIPS64 and CPU_MIPS32 variables are supposed to be able to
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distinguish broadly between 64-bit and 32-bit MIPS CPUs. However, they
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weren't selected by the specialty CPUs, Octeon and Loongson, which meant
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it was possible to hit a weird state of:
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MIPS=y, CONFIG_64BIT=y, CPU_MIPS64=n
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This commit rectifies the issue by having CPU_MIPS64 be selected when
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the missing Octeon or Loongson models are selected.
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Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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Cc: Ralf Baechle <ralf@linux-mips.org>
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Cc: George Cherian <gcherian@marvell.com>
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Cc: Huacai Chen <chenhuacai@kernel.org>
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Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
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Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
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---
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arch/mips/Kconfig | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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2021-12-05 16:43:36 +00:00
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@@ -2041,7 +2041,8 @@ config CPU_MIPS32
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kernel: 5.4: import wireguard backport
Rather than using the clunky, old, slower wireguard-linux-compat out of
tree module, this commit does a patch-by-patch backport of upstream's
wireguard to 5.4. This specific backport is in widespread use, being
part of SUSE's enterprise kernel, Oracle's enterprise kernel, Google's
Android kernel, Gentoo's distro kernel, and probably more I've forgotten
about. It's definately the "more proper" way of adding wireguard to a
kernel than the ugly compat.h hell of the wireguard-linux-compat repo.
And most importantly for OpenWRT, it allows using the same module
configuration code for 5.10 as for 5.4, with no need for bifurcation.
These patches are from the backport tree which is maintained in the
open here: https://git.zx2c4.com/wireguard-linux/log/?h=backport-5.4.y
I'll be sending PRs to update this as needed.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
(cherry picked from commit 3888fa78802354ab7bbd19b7d061fd80a16ce06b)
(cherry picked from commit d54072587146dd0db9bb52b513234d944edabda3)
(cherry picked from commit 196f3d586f11d96ba4ab60068cfb12420bcd20fd)
(cherry picked from commit 3500fd7938a6d0c0e320295f0aa2fa34b1ebc08d)
(cherry picked from commit 23b801d3ba57e34cc609ea40982c7fbed08164e9)
(cherry picked from commit 0c0cb97da7f5cc06919449131dd57ed805f8f78d)
(cherry picked from commit 2a27f6f90a430342cdbe84806e8b10acff446a2d)
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
2021-02-19 13:29:04 +00:00
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config CPU_MIPS64
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bool
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- default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
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+ default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 || \
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+ CPU_LOONGSON64 || CPU_CAVIUM_OCTEON
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#
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# These indicate the revision of the architecture
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