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75 lines
2.4 KiB
Diff
75 lines
2.4 KiB
Diff
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From 95e4dfbf33dc0a0843ba20db811f7ea271235e1e Mon Sep 17 00:00:00 2001
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From: Kewei Xu <kewei.xu@mediatek.com>
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Date: Sun, 10 Oct 2021 15:05:12 +0800
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Subject: [PATCH 01/16] i2c: mediatek: Reset the handshake signal between i2c
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and dma
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Due to changes in the hardware design of the handshaking signal
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between i2c and dma, it is necessary to reset the handshaking
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signal before each transfer to ensure that the multi-msgs can
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be transferred correctly.
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Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
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Reviewed-by: Qii Wang <qii.wang@mediatek.com>
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Signed-off-by: Wolfram Sang <wsa@kernel.org>
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---
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drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/drivers/i2c/busses/i2c-mt65xx.c
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+++ b/drivers/i2c/busses/i2c-mt65xx.c
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@@ -15,6 +15,7 @@
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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+#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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@@ -49,6 +50,8 @@
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#define I2C_RD_TRANAC_VALUE 0x0001
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#define I2C_SCL_MIS_COMP_VALUE 0x0000
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#define I2C_CHN_CLR_FLAG 0x0000
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+#define I2C_RELIABILITY 0x0010
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+#define I2C_DMAACK_ENABLE 0x0008
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#define I2C_DMA_CON_TX 0x0000
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#define I2C_DMA_CON_RX 0x0001
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@@ -851,6 +854,7 @@ static int mtk_i2c_do_transfer(struct mt
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u16 restart_flag = 0;
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u16 dma_sync = 0;
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u32 reg_4g_mode;
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+ u32 reg_dma_reset;
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u8 *dma_rd_buf = NULL;
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u8 *dma_wr_buf = NULL;
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dma_addr_t rpaddr = 0;
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@@ -864,6 +868,28 @@ static int mtk_i2c_do_transfer(struct mt
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reinit_completion(&i2c->msg_complete);
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+ if (i2c->dev_comp->apdma_sync &&
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+ i2c->op != I2C_MASTER_WRRD && num > 1) {
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+ mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL);
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+ writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
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+ i2c->pdmabase + OFFSET_RST);
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+
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+ ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
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+ reg_dma_reset,
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+ !(reg_dma_reset & I2C_DMA_WARM_RST),
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+ 0, 100);
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+ if (ret) {
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+ dev_err(i2c->dev, "DMA warm reset timeout\n");
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+ return -ETIMEDOUT;
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+ }
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+
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+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
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+ mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
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+ mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
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+ mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
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+ OFFSET_DEBUGCTRL);
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+ }
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+
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control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
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~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
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if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
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