2018-06-15 15:27:51 +00:00
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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2024-02-07 13:48:43 +00:00
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#include <dt-bindings/leds/common.h>
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2018-06-15 15:27:51 +00:00
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/ {
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compatible = "elecom,wrc-1167ghbk2-s", "mediatek,mt7621-soc";
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model = "ELECOM WRC-1167GHBK2-S";
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2018-07-16 08:27:22 +00:00
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aliases {
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2018-08-28 04:54:27 +00:00
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led-boot = &led_power_green;
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led-failsafe = &led_power_green;
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led-running = &led_power_green;
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led-upgrade = &led_power_green;
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2018-07-16 08:27:22 +00:00
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};
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2018-12-30 11:42:53 +00:00
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leds {
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2018-06-15 15:27:51 +00:00
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compatible = "gpio-leds";
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wlan2g {
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2020-09-27 17:40:51 +00:00
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label = "white:wlan2g";
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
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2019-06-27 03:27:27 +00:00
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linux,default-trigger = "phy0radio";
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2018-06-15 15:27:51 +00:00
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};
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wlan5g {
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2020-09-27 17:40:51 +00:00
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label = "white:wlan5g";
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
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2018-06-15 15:27:51 +00:00
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};
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2018-07-16 08:27:22 +00:00
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led_power_green: power_green {
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2024-02-07 13:48:43 +00:00
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_GREEN>;
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
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2018-06-15 15:27:51 +00:00
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};
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power_blue {
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2024-02-07 13:48:43 +00:00
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_BLUE>;
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
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2018-06-15 15:27:51 +00:00
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};
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wps {
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2024-02-07 13:48:43 +00:00
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function = LED_FUNCTION_WPS;
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color = <LED_COLOR_ID_RED>;
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
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2018-06-15 15:27:51 +00:00
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};
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power_red {
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2024-02-07 13:48:43 +00:00
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_RED>;
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
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2018-06-15 15:27:51 +00:00
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};
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};
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2018-12-30 11:17:25 +00:00
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keys {
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2019-09-20 12:03:02 +00:00
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compatible = "gpio-keys";
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2018-06-15 15:27:51 +00:00
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reset {
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label = "reset";
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
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2018-06-15 15:27:51 +00:00
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps";
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2020-03-03 21:22:24 +00:00
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gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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2018-06-15 15:27:51 +00:00
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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};
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2020-03-18 15:38:58 +00:00
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&gmac0 {
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2023-11-08 03:39:00 +00:00
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nvmem-cells = <&macaddr_factory_e000 0>;
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2021-04-02 21:50:02 +00:00
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nvmem-cell-names = "mac-address";
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2018-06-15 15:27:51 +00:00
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};
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2022-07-05 22:20:32 +00:00
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&gmac1 {
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status = "okay";
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label = "wan";
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phy-handle = <ðphy0>;
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nvmem-cells = <&macaddr_factory_e006>;
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nvmem-cell-names = "mac-address";
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};
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ramips: mt7621-dts: describe switch PHYs and adjust PHY muxing
Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide
direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO
bus the switch listens on. The PHY muxing feature makes use of this.
This is problematic as the PHY may be attached before the switch is
initialised, in which case, the PHY will fail to be attached.
Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration
of switch MDIO bus") on mainline Linux, we can describe the switch PHYs on
the MDIO bus of the switch on the device tree.
When the PHY is described this way, the switch will be initialised first,
then the switch MDIO bus will be registered. Only after these steps, the
PHY will be attached.
Describe the switch PHYs on mt7621.dtsi and remove defining the switch PHY
on the SoC's mdio bus node. When the PHY muxing is in use, the interrupts
for the muxed PHY won't work, therefore delete the "interrupts" property on
the devices where the PHY muxing feature is in use.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
2024-04-28 19:52:51 +00:00
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ðphy0 {
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/delete-property/ interrupts;
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2022-07-05 22:20:32 +00:00
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};
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2020-03-18 15:38:58 +00:00
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&switch0 {
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ports {
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port@1 {
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status = "okay";
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label = "lan4";
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};
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port@2 {
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status = "okay";
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label = "lan3";
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};
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port@3 {
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status = "okay";
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label = "lan2";
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};
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port@4 {
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status = "okay";
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label = "lan1";
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};
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};
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};
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2018-06-15 15:27:51 +00:00
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&spi0 {
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status = "okay";
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2020-05-07 14:15:27 +00:00
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flash@0 {
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2018-06-15 15:27:51 +00:00
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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2018-08-01 20:32:34 +00:00
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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2024-02-17 14:10:10 +00:00
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partition@40000 {
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2018-08-01 20:32:34 +00:00
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x4da8>;
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};
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macaddr_factory_e000: macaddr@e000 {
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2023-11-08 03:39:00 +00:00
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compatible = "mac-base";
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2023-11-07 23:55:58 +00:00
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reg = <0xe000 0x6>;
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2023-11-08 03:39:00 +00:00
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#nvmem-cell-cells = <1>;
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2023-11-07 23:55:58 +00:00
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};
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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macaddr_factory_e006: macaddr@e006 {
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reg = <0xe006 0x6>;
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};
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2023-10-02 02:12:02 +00:00
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};
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2018-08-01 20:32:34 +00:00
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};
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partition@50000 {
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2018-11-28 03:28:35 +00:00
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compatible = "denx,uimage";
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2018-08-01 20:32:34 +00:00
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label = "firmware";
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reg = <0x50000 0xf20000>;
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};
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partition@f70000 {
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label = "user_data";
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reg = <0xf70000 0x80000>;
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read-only;
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};
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partition@ff0000 {
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label = "NVRAM";
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reg = <0xff0000 0x10000>;
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read-only;
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};
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2018-06-15 15:27:51 +00:00
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};
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};
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};
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2019-12-22 20:26:01 +00:00
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&state_default {
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gpio {
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2020-03-13 13:27:03 +00:00
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groups = "i2c", "uart3", "jtag", "wdt";
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function = "gpio";
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2018-06-15 15:27:51 +00:00
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};
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};
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&pcie {
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status = "okay";
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2019-06-27 03:27:27 +00:00
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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2023-11-08 03:39:00 +00:00
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nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_e000 1>;
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2023-10-02 02:12:02 +00:00
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nvmem-cell-names = "eeprom", "mac-address";
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2019-06-27 03:27:27 +00:00
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};
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2018-06-15 15:27:51 +00:00
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};
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&xhci {
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status = "disabled";
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};
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