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53 lines
1.8 KiB
Diff
53 lines
1.8 KiB
Diff
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From 0cb2a8f3456ff1cc51d571e287a48e8fddc98ec2 Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Sat, 31 Dec 2022 08:40:41 +0100
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Subject: PCI: mt7621: Delay phy ports initialization
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Some devices like ZBT WE1326 and ZBT WF3526-P and some Netgear models need
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to delay phy port initialization after calling the mt7621_pcie_init_port()
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driver function to get into reliable boots for both warm and hard resets.
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The delay required to detect the ports seems to be in the range [75-100]
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milliseconds.
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If the ports are not detected the controller is not functional.
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There is no datasheet or something similar to really understand why this
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extra delay is needed only for these devices and it is not for most of
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the boards that are built on mt7621 SoC.
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This issue has been reported by openWRT community and the complete
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discussion is in [0]. The 100 milliseconds delay has been tested in all
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devices to validate it.
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Add the extra 100 milliseconds delay to fix the issue.
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[0]: https://github.com/openwrt/openwrt/pull/11220
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Link: https://lore.kernel.org/r/20221231074041.264738-1-sergio.paracuellos@gmail.com
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Fixes: 2bdd5238e756 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver")
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
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---
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drivers/pci/controller/pcie-mt7621.c | 2 ++
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1 file changed, 2 insertions(+)
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--- a/drivers/pci/controller/pcie-mt7621.c
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+++ b/drivers/pci/controller/pcie-mt7621.c
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@@ -58,6 +58,7 @@
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#define PCIE_PORT_LINKUP BIT(0)
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#define PCIE_PORT_CNT 3
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+#define INIT_PORTS_DELAY_MS 100
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#define PERST_DELAY_MS 100
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/**
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@@ -374,6 +375,7 @@ static int mt7621_pcie_init_ports(struct
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}
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}
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+ msleep(INIT_PORTS_DELAY_MS);
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mt7621_pcie_reset_ep_deassert(pcie);
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tmp = NULL;
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