2022-01-10 01:12:45 +00:00
|
|
|
From a29a7d01cd778854e08108461cba321a63d98871 Mon Sep 17 00:00:00 2001
|
|
|
|
|
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
|
|
|
|
Date: Fri, 2 Jul 2021 16:39:47 +0200
|
|
|
|
|
Subject: [PATCH] PCI: aardvark: Fix reading MSI interrupt number
|
|
|
|
|
MIME-Version: 1.0
|
|
|
|
|
Content-Type: text/plain; charset=UTF-8
|
|
|
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
|
|
|
|
|
|
In advk_pcie_handle_msi() the authors expect that when bit i in the W1C
|
|
|
|
|
register PCIE_MSI_STATUS_REG is cleared, the PCIE_MSI_PAYLOAD_REG is
|
|
|
|
|
updated to contain the MSI number corresponding to index i.
|
|
|
|
|
|
|
|
|
|
Experiments show that this is not so, and instead PCIE_MSI_PAYLOAD_REG
|
|
|
|
|
always contains the number of the last received MSI, overall.
|
|
|
|
|
|
|
|
|
|
Do not read PCIE_MSI_PAYLOAD_REG register for determining MSI interrupt
|
|
|
|
|
number. Since Aardvark already forbids more than 32 interrupts and uses
|
|
|
|
|
own allocated hwirq numbers, the msi_idx already corresponds to the
|
|
|
|
|
received MSI number.
|
|
|
|
|
|
|
|
|
|
Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
|
|
|
|
|
Signed-off-by: Pali Rohár <pali@kernel.org>
|
|
|
|
|
Signed-off-by: Marek Behún <kabel@kernel.org>
|
|
|
|
|
---
|
|
|
|
|
drivers/pci/controller/pci-aardvark.c | 13 ++++++-------
|
|
|
|
|
1 file changed, 6 insertions(+), 7 deletions(-)
|
|
|
|
|
|
|
|
|
|
--- a/drivers/pci/controller/pci-aardvark.c
|
|
|
|
|
+++ b/drivers/pci/controller/pci-aardvark.c
|
2022-04-13 20:25:50 +00:00
|
|
|
@@ -1391,7 +1391,7 @@ static void advk_pcie_remove_irq_domain(
|
2022-01-10 01:12:45 +00:00
|
|
|
static void advk_pcie_handle_msi(struct advk_pcie *pcie)
|
|
|
|
|
{
|
|
|
|
|
u32 msi_val, msi_mask, msi_status, msi_idx;
|
|
|
|
|
- u16 msi_data;
|
|
|
|
|
+ int virq;
|
|
|
|
|
|
|
|
|
|
msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
|
|
|
|
|
msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
|
2022-04-13 20:25:50 +00:00
|
|
|
@@ -1401,13 +1401,12 @@ static void advk_pcie_handle_msi(struct
|
2022-01-10 01:12:45 +00:00
|
|
|
if (!(BIT(msi_idx) & msi_status))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
- /*
|
|
|
|
|
- * msi_idx contains bits [4:0] of the msi_data and msi_data
|
|
|
|
|
- * contains 16bit MSI interrupt number
|
|
|
|
|
- */
|
|
|
|
|
advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
|
|
|
|
|
- msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK;
|
|
|
|
|
- generic_handle_irq(msi_data);
|
|
|
|
|
+ virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx);
|
|
|
|
|
+ if (virq)
|
|
|
|
|
+ generic_handle_irq(virq);
|
|
|
|
|
+ else
|
|
|
|
|
+ dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
|
