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130 lines
4.7 KiB
Diff
130 lines
4.7 KiB
Diff
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From 5f07b26e85dc86f017833ea745ff4e5b420280cd Mon Sep 17 00:00:00 2001
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From: Miquel Raynal <miquel.raynal@bootlin.com>
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Date: Fri, 4 Oct 2019 16:27:31 +0200
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Subject: [PATCH] arm64: dts: marvell: Externalize PCIe macros from CP11x file
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PCIe macros are specific to CP110 and will not fit CP115
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constraints. To keep the same way the files are organized, just move
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some macros out of the CP11x generic file and define them directly in
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SoC DTSI, instead of defining single addresses in the SoC DTSI and
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reusing them in macros.
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In the end:
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* CP11X_PCIE_MEM_BASE SoC define is dropped
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* CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the
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SoC files as it replaces the above definition.
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* As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with
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newer SoCs, we put it in the SoC files as well.
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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---
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arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++--
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arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 12 ++++++++----
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arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 9 ++++-----
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3 files changed, 16 insertions(+), 11 deletions(-)
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--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
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@@ -19,7 +19,8 @@
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*/
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#define CP11X_NAME cp0
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#define CP11X_BASE f2000000
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-#define CP11X_PCIE_MEM_BASE 0xf6000000
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+#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
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+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
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#define CP11X_PCIE0_BASE f2600000
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#define CP11X_PCIE1_BASE f2620000
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#define CP11X_PCIE2_BASE f2640000
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@@ -28,7 +29,8 @@
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#undef CP11X_NAME
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#undef CP11X_BASE
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-#undef CP11X_PCIE_MEM_BASE
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+#undef CP11X_PCIEx_MEM_BASE
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+#undef CP11X_PCIEx_MEM_SIZE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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#undef CP11X_PCIE2_BASE
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--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
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@@ -21,7 +21,8 @@
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*/
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#define CP11X_NAME cp0
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#define CP11X_BASE f2000000
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-#define CP11X_PCIE_MEM_BASE 0xf6000000
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+#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
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+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
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#define CP11X_PCIE0_BASE f2600000
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#define CP11X_PCIE1_BASE f2620000
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#define CP11X_PCIE2_BASE f2640000
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@@ -30,7 +31,8 @@
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#undef CP11X_NAME
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#undef CP11X_BASE
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-#undef CP11X_PCIE_MEM_BASE
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+#undef CP11X_PCIEx_MEM_BASE
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+#undef CP11X_PCIEx_MEM_SIZE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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#undef CP11X_PCIE2_BASE
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@@ -40,7 +42,8 @@
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*/
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#define CP11X_NAME cp1
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#define CP11X_BASE f4000000
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-#define CP11X_PCIE_MEM_BASE 0xfa000000
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+#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
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+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
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#define CP11X_PCIE0_BASE f4600000
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#define CP11X_PCIE1_BASE f4620000
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#define CP11X_PCIE2_BASE f4640000
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@@ -49,7 +52,8 @@
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#undef CP11X_NAME
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#undef CP11X_BASE
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-#undef CP11X_PCIE_MEM_BASE
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+#undef CP11X_PCIEx_MEM_BASE
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+#undef CP11X_PCIEx_MEM_SIZE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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#undef CP11X_PCIE2_BASE
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--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
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@@ -10,8 +10,7 @@
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#include "armada-common.dtsi"
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-#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
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-#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
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+#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
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/ {
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/*
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@@ -507,7 +506,7 @@
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bus-range = <0 0xff>;
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/* non-prefetchable memory */
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- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
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+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
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@@ -531,7 +530,7 @@
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bus-range = <0 0xff>;
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/* non-prefetchable memory */
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- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
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+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
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@@ -556,7 +555,7 @@
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bus-range = <0 0xff>;
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/* non-prefetchable memory */
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- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
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+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
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