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77 lines
2.0 KiB
Diff
77 lines
2.0 KiB
Diff
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From ec0d1899b035700a657721761ff6370b940450ab Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 3 Mar 2021 10:51:43 +0800
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Subject: [PATCH 18/21] board: mt7622: use new spi-nand driver
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Enable new spi-nand driver support for mt7622_rfb_defconfig
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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arch/arm/dts/mt7622-rfb.dts | 7 +++++++
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arch/arm/dts/mt7622.dtsi | 16 ++++++++++++++++
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configs/mt7622_rfb_defconfig | 5 +++++
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3 files changed, 28 insertions(+)
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--- a/arch/arm/dts/mt7622-rfb.dts
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+++ b/arch/arm/dts/mt7622-rfb.dts
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@@ -188,6 +188,13 @@
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};
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};
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+&snand {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&snfi_pins>;
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+ status = "okay";
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+ quad-spi;
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+};
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+
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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--- a/arch/arm/dts/mt7622.dtsi
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+++ b/arch/arm/dts/mt7622.dtsi
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@@ -53,6 +53,22 @@
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#size-cells = <0>;
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};
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+ snand: snand@1100d000 {
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+ compatible = "mediatek,mt7622-snand";
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+ reg = <0x1100d000 0x1000>,
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+ <0x1100e000 0x1000>;
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+ reg-names = "nfi", "ecc";
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+ clocks = <&pericfg CLK_PERI_NFI_PD>,
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+ <&pericfg CLK_PERI_SNFI_PD>,
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+ <&pericfg CLK_PERI_NFIECC_PD>;
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+ clock-names = "nfi_clk", "pad_clk", "ecc_clk";
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+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
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+ <&topckgen CLK_TOP_NFI_INFRA_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
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+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
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+ status = "disabled";
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+ };
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+
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snor: snor@11014000 {
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compatible = "mediatek,mtk-snor";
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reg = <0x11014000 0x1000>;
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--- a/configs/mt7622_rfb_defconfig
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+++ b/configs/mt7622_rfb_defconfig
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@@ -15,6 +15,7 @@ CONFIG_LOG=y
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CONFIG_SYS_PROMPT="MT7622> "
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CONFIG_CMD_BOOTMENU=y
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CONFIG_CMD_MMC=y
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+CONFIG_CMD_MTD=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_SF_TEST=y
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CONFIG_CMD_PING=y
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@@ -28,6 +29,10 @@ CONFIG_CLK=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_MMC_MTK=y
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+CONFIG_MTD=y
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+CONFIG_DM_MTD=y
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+CONFIG_MTK_SPI_NAND=y
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+CONFIG_MTK_SPI_NAND_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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