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openwrt/target/linux/ath79/dts/qca9557_engenius_ecb1200.dts

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ath79: add support for Senao Engenius ECB1200 FCC ID: A8J-ECB1200 Engenius ECB1200 is an indoor wireless access point with a GbE port, 2.4 GHz and 5 GHz wireless, external antennas, and 802.3af PoE. **Specification:** - QCA9557 SOC MIPS, 2.4 GHz (2x2) - QCA9882 WLAN PCIe card, 5 GHz (2x2) - AR8035-A switch RGMII, GbE with 802.3af PoE, 25 MHz clock - 40 MHz reference clock - 16 MB FLASH 25L12845EMI-10G - 2x 64 MB RAM 1538ZFZ V59C1512164QEJ25 - UART at JP1 (unpopulated, RX shorted to ground) - 4 external antennas - 4 LEDs, 1 button (power, eth, wifi2g, wifi5g) (reset) **MAC addresses:** MAC Addresses are labeled as ETH and 5GHZ U-boot environment has the vendor MAC addresses MAC addresses in ART do not match vendor eth0 ETH *:5c u-boot-env ethaddr phy0 5GHZ *:5d u-boot-env athaddr ---- ---- ???? art 0x0/0x6 **Installation:** Method 1: Firmware upgrade page: OEM webpage at 192.168.1.1 username and password "admin" Navigate to "Firmware" page from left pane Click Browse and select the factory.bin image Upload and verify checksum Click Continue to confirm and wait 3 minutes Method 2: Serial to load Failsafe webpage: After connecting to serial console and rebooting... Interrupt uboot with any key pressed rapidly (see TFTP recovery) perform a sysupgrade **Serial Access:** the RX line on the board for UART is shorted to ground by resistor R176 therefore it must be removed to use the console but it is not necessary to remove to view boot log optionally, R175 can be replaced with a solder bridge short the resistors R175 and R176 are next to the UART pinout at JP1 **Return to OEM:** If you have a serial cable, see Serial Failsafe instructions Unlike most Engenius boards, this does not have a 'failsafe' image the only way to return to OEM is TFTP or serial access to u-boot **TFTP recovery:** Unlike most Engenius boards, TFTP is reliable here rename initramfs-kernel.bin to 'ap.bin' make the file available on a TFTP server at 192.168.1.10 power board while holding or pressing reset button repeatedly or with serial access: run `tftpboot` or `run factory_boot` with initramfs-kernel.bin then `bootm` with the load address **Format of OEM firmware image:** The OEM software of ECB1200 is a heavily modified version of Openwrt Altitude Adjustment 12.09. This Engenius board, like ECB1750, uses a proprietary header with a unique Product ID. The header for factory.bin is generated by the mksenaofw program included in openwrt. **Note on PLL-data cells:** The default PLL register values will not work because of the AR8035 switch between the SOC and the ethernet port. For QCA955x series, the PLL registers for eth0 and eth1 can be see in the DTSI as 0x28 and 0x48 respectively. Therefore the PLL registers can be read from uboot for each link speed after attempting tftpboot or another network action using that link speed with `md 0x18050028 1` and `md 0x18050048 1`. However the registers that u-boot sets are not ideal and sometimes wrong... the at803x driver supports setting the RGMII clock/data delay on the PHY side. This way the pll-data register only needs to handle invert and phase. for this board clock invert is needed on the MAC side all link speeds functional Signed-off-by: Michael Pratt <mcpratt@pm.me>
2020-11-01 01:23:33 +00:00
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
ath79: create common DTSI for ECB1200 and ECB1750 These boards are sister boards exactly the same hardware except that ECB1200 has: - QCA9557 - 2 RF circuits/antennas per band instead of 3 - a resistor blocking UART RX line Tested-by: sven friedmann <sf.openwrt@okay.ms> Signed-off-by: Michael Pratt <mcpratt@pm.me>
2020-11-26 23:57:31 +00:00
#include "qca955x_engenius_ecb1xxx.dtsi"
ath79: add support for Senao Engenius ECB1200 FCC ID: A8J-ECB1200 Engenius ECB1200 is an indoor wireless access point with a GbE port, 2.4 GHz and 5 GHz wireless, external antennas, and 802.3af PoE. **Specification:** - QCA9557 SOC MIPS, 2.4 GHz (2x2) - QCA9882 WLAN PCIe card, 5 GHz (2x2) - AR8035-A switch RGMII, GbE with 802.3af PoE, 25 MHz clock - 40 MHz reference clock - 16 MB FLASH 25L12845EMI-10G - 2x 64 MB RAM 1538ZFZ V59C1512164QEJ25 - UART at JP1 (unpopulated, RX shorted to ground) - 4 external antennas - 4 LEDs, 1 button (power, eth, wifi2g, wifi5g) (reset) **MAC addresses:** MAC Addresses are labeled as ETH and 5GHZ U-boot environment has the vendor MAC addresses MAC addresses in ART do not match vendor eth0 ETH *:5c u-boot-env ethaddr phy0 5GHZ *:5d u-boot-env athaddr ---- ---- ???? art 0x0/0x6 **Installation:** Method 1: Firmware upgrade page: OEM webpage at 192.168.1.1 username and password "admin" Navigate to "Firmware" page from left pane Click Browse and select the factory.bin image Upload and verify checksum Click Continue to confirm and wait 3 minutes Method 2: Serial to load Failsafe webpage: After connecting to serial console and rebooting... Interrupt uboot with any key pressed rapidly (see TFTP recovery) perform a sysupgrade **Serial Access:** the RX line on the board for UART is shorted to ground by resistor R176 therefore it must be removed to use the console but it is not necessary to remove to view boot log optionally, R175 can be replaced with a solder bridge short the resistors R175 and R176 are next to the UART pinout at JP1 **Return to OEM:** If you have a serial cable, see Serial Failsafe instructions Unlike most Engenius boards, this does not have a 'failsafe' image the only way to return to OEM is TFTP or serial access to u-boot **TFTP recovery:** Unlike most Engenius boards, TFTP is reliable here rename initramfs-kernel.bin to 'ap.bin' make the file available on a TFTP server at 192.168.1.10 power board while holding or pressing reset button repeatedly or with serial access: run `tftpboot` or `run factory_boot` with initramfs-kernel.bin then `bootm` with the load address **Format of OEM firmware image:** The OEM software of ECB1200 is a heavily modified version of Openwrt Altitude Adjustment 12.09. This Engenius board, like ECB1750, uses a proprietary header with a unique Product ID. The header for factory.bin is generated by the mksenaofw program included in openwrt. **Note on PLL-data cells:** The default PLL register values will not work because of the AR8035 switch between the SOC and the ethernet port. For QCA955x series, the PLL registers for eth0 and eth1 can be see in the DTSI as 0x28 and 0x48 respectively. Therefore the PLL registers can be read from uboot for each link speed after attempting tftpboot or another network action using that link speed with `md 0x18050028 1` and `md 0x18050048 1`. However the registers that u-boot sets are not ideal and sometimes wrong... the at803x driver supports setting the RGMII clock/data delay on the PHY side. This way the pll-data register only needs to handle invert and phase. for this board clock invert is needed on the MAC side all link speeds functional Signed-off-by: Michael Pratt <mcpratt@pm.me>
2020-11-01 01:23:33 +00:00
/ {
compatible = "engenius,ecb1200", "qca,qca9557";
model = "EnGenius ECB1200";
};
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