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33 lines
1.2 KiB
Diff
33 lines
1.2 KiB
Diff
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From beda1bbdb19baa8319ed81fa370fe0c5b91d05df Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <f.fainelli@gmail.com>
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Date: Tue, 26 Oct 2021 11:36:22 -0700
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Subject: [PATCH] ARM: dts: BCM5301X: Fix I2C controller interrupt
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The I2C interrupt controller line is off by 32 because the datasheet
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describes interrupt inputs into the GIC which are for Shared Peripheral
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Interrupts and are starting at offset 32. The ARM GIC binding expects
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the SPI interrupts to be numbered from 0 relative to the SPI base.
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Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT")
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
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index f92089290ccd..ec5de636796e 100644
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -408,7 +408,7 @@ uart2: serial@18008000 {
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i2c0: i2c@18009000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x18009000 0x50>;
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- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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--
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2.25.1
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