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83 lines
2.6 KiB
Diff
83 lines
2.6 KiB
Diff
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From 94c7f8af2c0a399c8aa66f2522b60c5784b5be6c Mon Sep 17 00:00:00 2001
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From: Kewei Xu <kewei.xu@mediatek.com>
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Date: Sat, 6 Aug 2022 18:02:49 +0800
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Subject: [PATCH 10/16] i2c: mediatek: add i2c compatible for MT8188
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Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since
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MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94.
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Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Reviewed-by: Qii Wang <qii.wang@mediatek.com>
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Signed-off-by: Wolfram Sang <wsa@kernel.org>
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---
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drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++
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1 file changed, 43 insertions(+)
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--- a/drivers/i2c/busses/i2c-mt65xx.c
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+++ b/drivers/i2c/busses/i2c-mt65xx.c
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@@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = {
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[OFFSET_DCM_EN] = 0xf88,
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};
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+static const u16 mt_i2c_regs_v3[] = {
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+ [OFFSET_DATA_PORT] = 0x0,
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+ [OFFSET_INTR_MASK] = 0x8,
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+ [OFFSET_INTR_STAT] = 0xc,
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+ [OFFSET_CONTROL] = 0x10,
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+ [OFFSET_TRANSFER_LEN] = 0x14,
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+ [OFFSET_TRANSAC_LEN] = 0x18,
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+ [OFFSET_DELAY_LEN] = 0x1c,
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+ [OFFSET_TIMING] = 0x20,
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+ [OFFSET_START] = 0x24,
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+ [OFFSET_EXT_CONF] = 0x28,
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+ [OFFSET_LTIMING] = 0x2c,
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+ [OFFSET_HS] = 0x30,
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+ [OFFSET_IO_CONFIG] = 0x34,
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+ [OFFSET_FIFO_ADDR_CLR] = 0x38,
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+ [OFFSET_SDA_TIMING] = 0x3c,
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+ [OFFSET_TRANSFER_LEN_AUX] = 0x44,
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+ [OFFSET_CLOCK_DIV] = 0x48,
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+ [OFFSET_SOFTRESET] = 0x50,
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+ [OFFSET_MULTI_DMA] = 0x8c,
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+ [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
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+ [OFFSET_SLAVE_ADDR] = 0x94,
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+ [OFFSET_DEBUGSTAT] = 0xe4,
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+ [OFFSET_DEBUGCTRL] = 0xe8,
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+ [OFFSET_FIFO_STAT] = 0xf4,
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+ [OFFSET_FIFO_THRESH] = 0xf8,
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+ [OFFSET_DCM_EN] = 0xf88,
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+};
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+
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struct mtk_i2c_compatible {
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const struct i2c_adapter_quirks *quirks;
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const u16 *regs;
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@@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible m
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.max_dma_support = 36,
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};
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+static const struct mtk_i2c_compatible mt8188_compat = {
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+ .regs = mt_i2c_regs_v3,
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+ .pmic_i2c = 0,
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+ .dcm = 0,
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+ .auto_restart = 1,
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+ .aux_len_reg = 1,
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+ .timing_adjust = 1,
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+ .dma_sync = 0,
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+ .ltiming_adjust = 1,
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+ .apdma_sync = 1,
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+ .max_dma_support = 36,
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+};
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+
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static const struct mtk_i2c_compatible mt8192_compat = {
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.quirks = &mt8183_i2c_quirks,
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.regs = mt_i2c_regs_v2,
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@@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c
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{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
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{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
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{ .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
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+ { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
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{ .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
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{}
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};
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