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61 lines
2.0 KiB
Diff
61 lines
2.0 KiB
Diff
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From 8d61eb953496aba51b94dac07c31c7e069c784bd Mon Sep 17 00:00:00 2001
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From: Chunfeng Yun <chunfeng.yun@mediatek.com>
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Date: Wed, 27 May 2015 19:47:58 +0800
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Subject: [PATCH 44/76] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs
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add a DT binding documentation of usb3.0 phy for MT65xx
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SoCs from Mediatek.
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Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
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---
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.../devicetree/bindings/usb/mt65xx-u3phy.txt | 37 ++++++++++++++++++++
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1 file changed, 37 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
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diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
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new file mode 100644
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index 0000000..b0b91b0
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt
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@@ -0,0 +1,37 @@
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+MT65xx U3PHY
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+
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+The device node for Mediatek SOC usb3.0 phy
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+
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+Required properties:
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+ - compatible : Should be "mediatek,mt8173-u3phy"
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+ - reg : Offset and length of registers, the first is for mac domain,
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+ another for phy domain
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+ - power-domains: to enable usb's mtcmos
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+ - reg-vusb33-supply: regulator of usb avdd3.3v
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+ - clocks : must support all clocks that phy need
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+ - clock-names: should be "wakeup_deb_p0", "wakeup_deb_p1" for wakeup
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+ debounce control clocks, "sys_mac" for sys and mac clocks and
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+ "u3phya_ref" for u3phya reference clock.
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+
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+Optional properties:
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+ - disable-usb2-p1 : disable port1 of usb2.0 which has two ports.
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+ - reg-p1-vbus-supply : regulator of port1's vbus;
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+
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+Example:
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+
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+u3phy: usb-phy@11271000 {
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+ compatible = "mediatek,mt8173-u3phy";
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+ reg = <0 0x11271000 0 0x3000>,
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+ <0 0x11280000 0 0x20000>;
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+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
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+ reg-vusb33-supply = <&mt6397_usb_reg>;
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+ clocks = <&perisys PERI_USB0>,
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+ <&perisys PERI_USB1>,
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+ <&topckgen CLK_TOP_USB30_SEL>,
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+ <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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+ clock-names = "wakeup_deb_p0",
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+ "wakeup_deb_p1",
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+ "sys_mac",
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+ "u3phya_ref";
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+ disable-usb2-p1;
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+};
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--
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1.7.10.4
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