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65 lines
2.2 KiB
Diff
65 lines
2.2 KiB
Diff
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From e6e0631fdeb0cd7d4c50e629b4b298e0b76e885b Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Wed, 4 Oct 2023 16:02:39 +0100
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Subject: [PATCH] vc4/drm: Remove the clear of SCALER_DISPBKGND_FILL
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Since "drm/vc4: hvs: Support BCM2712 HVS" booting Pi4
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with dual 4kp30 displays connected fails with:
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vc4-drm gpu: [drm] *ERROR* [CRTC:107:pixelvalve-4] flip_done timed out
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It has been tracked down to the referenced commit adding a
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path to clear the SCALER_DISPBKGND_FILL when not required.
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Dual 4kp30 works with a core clock of 297MHz when background fill
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is enabled, but requires a higher value with it disabled.
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320MHz still fails, while 330MHz seems okay.
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Lets always enable background fill for Pi0-4.
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Fixes: e84da235223d ("drm/vc4: hvs: Support BCM2712 HVS")
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hvs.c | 20 +++++++++-----------
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1 file changed, 9 insertions(+), 11 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -1349,27 +1349,25 @@ void vc4_hvs_atomic_flush(struct drm_crt
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WARN_ON(!vc4_state->mm);
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WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm->mm_node.size);
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- if (enable_bg_fill) {
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+ if (vc4->gen >= VC4_GEN_6) {
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/* This sets a black background color fill, as is the case
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* with other DRM drivers.
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*/
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- if (vc4->gen >= VC4_GEN_6)
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+ if (enable_bg_fill)
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HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
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HVS_READ(SCALER6_DISPX_CTRL1(channel)) |
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SCALER6_DISPX_CTRL1_BGENB);
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else
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- HVS_WRITE(SCALER_DISPBKGNDX(channel),
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- HVS_READ(SCALER_DISPBKGNDX(channel)) |
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- SCALER_DISPBKGND_FILL);
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- } else {
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- if (vc4->gen >= VC4_GEN_6)
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HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
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HVS_READ(SCALER6_DISPX_CTRL1(channel)) &
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~SCALER6_DISPX_CTRL1_BGENB);
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- else
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- HVS_WRITE(SCALER_DISPBKGNDX(channel),
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- HVS_READ(SCALER_DISPBKGNDX(channel)) &
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- ~SCALER_DISPBKGND_FILL);
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+ } else {
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+ /* we can actually run with a lower core clock when background
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+ * fill is enabled on VC4_GEN_5 so leave it enabled always.
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+ */
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+ HVS_WRITE(SCALER_DISPBKGNDX(channel),
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+ HVS_READ(SCALER_DISPBKGNDX(channel)) |
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+ SCALER_DISPBKGND_FILL);
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}
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/* Only update DISPLIST if the CRTC was already running and is not
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