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58 lines
1.9 KiB
Diff
58 lines
1.9 KiB
Diff
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From 04f38d1a4db017f17e82442727b91ce03dd72759 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= <dgcbueu@gmail.com>
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Date: Thu, 20 Jun 2024 17:26:45 +0200
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Subject: [PATCH 4/4] mips: bmips: enable RAC on BMIPS4350
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The data RAC is left disabled by the bootloader in some SoCs, at least in
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the core it boots from.
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Enabling this feature increases the performance up to +30% depending on the
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task.
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Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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[ rework code and reduce code duplication ]
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Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/kernel/smp-bmips.c | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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--- a/arch/mips/kernel/smp-bmips.c
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+++ b/arch/mips/kernel/smp-bmips.c
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@@ -592,6 +592,7 @@ asmlinkage void __weak plat_wired_tlb_se
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void bmips_cpu_setup(void)
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{
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void __iomem __maybe_unused *cbr = bmips_cbr_addr;
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+ u32 __maybe_unused rac_addr;
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u32 __maybe_unused cfg;
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switch (current_cpu_type()) {
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@@ -620,6 +621,23 @@ void bmips_cpu_setup(void)
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__raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
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break;
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+ case CPU_BMIPS4350:
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+ rac_addr = BMIPS_RAC_CONFIG_1;
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+
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+ if (!(read_c0_brcm_cmt_local() & (1 << 31)))
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+ rac_addr = BMIPS_RAC_CONFIG;
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+
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+ /* Enable data RAC */
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+ cfg = __raw_readl(cbr + rac_addr);
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+ __raw_writel(cfg | 0xf, cbr + rac_addr);
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+ __raw_readl(cbr + rac_addr);
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+
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+ /* Flush stale data out of the readahead cache */
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+ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
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+ __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
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+ __raw_readl(cbr + BMIPS_RAC_CONFIG);
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+ break;
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+
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case CPU_BMIPS4380:
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/* CBG workaround for early BMIPS4380 CPUs */
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switch (read_c0_prid()) {
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