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27 lines
869 B
Diff
27 lines
869 B
Diff
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From 893368e64049fd770e55fffcc8758d2619dc337d Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Mon, 25 Jul 2022 16:33:13 +0800
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Subject: [PATCH 11/31] arm: dts: mt7622: force high-speed mode for uart
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The input clock for uart is too slow (25MHz) which introduces frequent data
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error on both receiving and transmitting even if the baudrate is 115200.
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Using high-speed can significantly solve this issue.
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Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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arch/arm/dts/mt7622.dtsi | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/arm/dts/mt7622.dtsi
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+++ b/arch/arm/dts/mt7622.dtsi
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@@ -191,6 +191,7 @@
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status = "disabled";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
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+ mediatek,force-highspeed;
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};
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mmc0: mmc@11230000 {
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