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31 lines
1.2 KiB
Diff
31 lines
1.2 KiB
Diff
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From 2038e0416518b30bb40857fbafa3733a6bae93ca Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
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Date: Tue, 26 May 2020 13:03:24 +0200
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Subject: [PATCH] MIPS: BCM63xx: fix 6328 boot selection bit
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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MISC_STRAP_BUS_BOOT_SEL_SHIFT is 18 according to Broadcom's GPL source code.
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Acked-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1367,8 +1367,8 @@
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#define MISC_STRAPBUS_6328_REG 0x240
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#define STRAPBUS_6328_FCVO_SHIFT 7
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#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
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-#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
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-#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
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+#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 18)
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+#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 18)
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/*************************************************************************
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* _REG relative to RSET_PCIE
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