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124 lines
3.8 KiB
Diff
124 lines
3.8 KiB
Diff
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From 47e161a7873b0891f4e01a69a839f6161d816ea8 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 25 Oct 2023 14:57:57 +0530
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Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ6018
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IPQ6018 SoC series comes in multiple SKU-s, and not all of them support
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high frequency OPP points.
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SoC itself does however have a single bit in QFPROM to indicate the CPU
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speed-bin.
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That bit is used to indicate frequency limit of 1.5GHz, but that alone is
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not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to
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limit it further.
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IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device
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will get created by NVMEM CPUFreq driver.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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[ Viresh: Fixed rebase conflict. ]
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Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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---
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drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
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drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++++++++++
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2 files changed, 59 insertions(+)
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--- a/drivers/cpufreq/cpufreq-dt-platdev.c
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+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
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@@ -163,6 +163,7 @@ static const struct of_device_id blockli
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{ .compatible = "ti,dra7", },
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{ .compatible = "ti,omap3", },
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+ { .compatible = "qcom,ipq6018", },
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{ .compatible = "qcom,ipq8064", },
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{ .compatible = "qcom,ipq8074", },
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{ .compatible = "qcom,apq8064", },
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--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
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+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
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@@ -36,6 +36,8 @@ enum ipq8074_versions {
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IPQ8074_ACORN_VERSION,
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};
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+#define IPQ6000_VERSION BIT(2)
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+
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struct qcom_cpufreq_drv;
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struct qcom_cpufreq_match_data {
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@@ -209,6 +211,57 @@ len_error:
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return ret;
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}
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+static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
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+ struct nvmem_cell *speedbin_nvmem,
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+ char **pvs_name,
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+ struct qcom_cpufreq_drv *drv)
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+{
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+ u32 msm_id;
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+ int ret;
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+ u8 *speedbin;
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+ *pvs_name = NULL;
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+
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+ ret = qcom_smem_get_soc_id(&msm_id);
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+ if (ret)
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+ return ret;
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+
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+ speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
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+ if (IS_ERR(speedbin))
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+ return PTR_ERR(speedbin);
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+
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+ switch (msm_id) {
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+ case QCOM_ID_IPQ6005:
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+ case QCOM_ID_IPQ6010:
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+ case QCOM_ID_IPQ6018:
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+ case QCOM_ID_IPQ6028:
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+ /* Fuse Value Freq BIT to set
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+ * ---------------------------------
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+ * 2’b0 No Limit BIT(0)
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+ * 2’b1 1.5 GHz BIT(1)
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+ */
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+ drv->versions = 1 << (unsigned int)(*speedbin);
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+ break;
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+ case QCOM_ID_IPQ6000:
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+ /*
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+ * IPQ6018 family only has one bit to advertise the CPU
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+ * speed-bin, but that is not enough for IPQ6000 which
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+ * is only rated up to 1.2GHz.
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+ * So for IPQ6000 manually set BIT(2) based on SMEM ID.
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+ */
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+ drv->versions = IPQ6000_VERSION;
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+ break;
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+ default:
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+ dev_err(cpu_dev,
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+ "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
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+ msm_id);
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+ drv->versions = IPQ6000_VERSION;
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+ break;
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+ }
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+
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+ kfree(speedbin);
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+ return 0;
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+}
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+
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static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
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struct nvmem_cell *speedbin_nvmem,
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char **pvs_name,
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@@ -265,6 +318,10 @@ static const struct qcom_cpufreq_match_d
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.get_version = qcom_cpufreq_ipq8074_name_version,
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};
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+static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
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+ .get_version = qcom_cpufreq_ipq6018_name_version,
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+};
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+
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static int qcom_cpufreq_probe(struct platform_device *pdev)
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{
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struct qcom_cpufreq_drv *drv;
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@@ -409,6 +466,7 @@ static const struct of_device_id qcom_cp
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{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
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{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
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{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
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+ { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
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{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
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{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
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{ .compatible = "qcom,apq8064", .data = &match_data_krait },
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