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40 lines
1.4 KiB
Diff
40 lines
1.4 KiB
Diff
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From 16993169c82c2c57e1df1e7f4598a7c2aa565fe2 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 7 Aug 2022 11:12:02 -0500
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Subject: [PATCH 104/117] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit
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last
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The A100 variant of the DPHY requires configuring the analog registers
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before setting the global enable bit. Since this order also works on the
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other variants, always use it, to minimize the differences between them.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
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+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
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@@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct
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SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
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SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
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- regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
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- SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
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- SUN6I_DPHY_GCTL_EN);
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-
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regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
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SUN6I_DPHY_ANA0_REG_PWS |
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SUN6I_DPHY_ANA0_REG_DMPC |
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@@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct
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SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
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SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
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+ regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
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+ SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
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+ SUN6I_DPHY_GCTL_EN);
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+
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return 0;
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}
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