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29 lines
1.3 KiB
Diff
29 lines
1.3 KiB
Diff
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From 52bffb91d40a3090ecf9138fadca97f77c99afa4 Mon Sep 17 00:00:00 2001
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From: Haiying Wang <Haiying.Wang@freescale.com>
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Date: Wed, 22 Apr 2015 13:09:47 -0400
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Subject: [PATCH 34/70] arm64: add support to remap kernel cacheable memory to
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userspace
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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Change-Id: I50ee4798a2929932fa9ff7c9cdb42cd1a215f77a
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Reviewed-on: http://git.am.freescale.net:8181/35488
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Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
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Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
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---
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arch/arm64/include/asm/pgtable.h | 3 +++
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1 file changed, 3 insertions(+)
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--- a/arch/arm64/include/asm/pgtable.h
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+++ b/arch/arm64/include/asm/pgtable.h
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@@ -389,6 +389,9 @@ static inline int has_transparent_hugepa
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
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#define pgprot_writecombine(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
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+#define pgprot_cached(prot) \
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+ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
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+ PTE_PXN | PTE_UXN)
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#define pgprot_device(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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