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106 lines
3.8 KiB
Diff
106 lines
3.8 KiB
Diff
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From 9a0e95e34e9c0a713ddfd48c3a88a20d2bdfd514 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <j4g8y7@gmail.com>
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Date: Fri, 11 Aug 2023 13:10:07 +0200
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Subject: [PATCH] net: phy: Introduce PSGMII PHY interface mode
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The PSGMII interface is similar to QSGMII. The main difference
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is that the PSGMII interface combines five SGMII lines into a
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single link while in QSGMII only four lines are combined.
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Similarly to the QSGMII, this interface mode might also needs
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special handling within the MAC driver.
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It is commonly used by Qualcomm with their QCA807x PHY series and
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modern WiSoC-s.
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Add definitions for the PHY layer to allow to express this type
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of connection between the MAC and PHY.
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Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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Documentation/networking/phy.rst | 4 ++++
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drivers/net/phy/phy-core.c | 2 ++
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drivers/net/phy/phylink.c | 3 +++
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include/linux/phy.h | 4 ++++
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4 files changed, 13 insertions(+)
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--- a/Documentation/networking/phy.rst
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+++ b/Documentation/networking/phy.rst
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@@ -323,6 +323,10 @@ Some of the interface modes are describe
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contrast with the 1000BASE-X phy mode used for Clause 38 and 39 PMDs, this
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interface mode has different autonegotiation and only supports full duplex.
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+``PHY_INTERFACE_MODE_PSGMII``
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+ This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
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+ SGMII lines into a single link compared to 4 on QSGMII.
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+
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Pause frames / flow control
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===========================
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--- a/drivers/net/phy/phy-core.c
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+++ b/drivers/net/phy/phy-core.c
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@@ -140,6 +140,8 @@ int phy_interface_num_ports(phy_interfac
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_QUSGMII:
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return 4;
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+ case PHY_INTERFACE_MODE_PSGMII:
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+ return 5;
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case PHY_INTERFACE_MODE_MAX:
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WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode");
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return 0;
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--- a/drivers/net/phy/phylink.c
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+++ b/drivers/net/phy/phylink.c
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@@ -187,6 +187,7 @@ static int phylink_interface_max_speed(p
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII:
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+ case PHY_INTERFACE_MODE_PSGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_QUSGMII:
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case PHY_INTERFACE_MODE_SGMII:
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@@ -448,6 +449,7 @@ unsigned long phylink_get_capabilities(p
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII:
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+ case PHY_INTERFACE_MODE_PSGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_QUSGMII:
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case PHY_INTERFACE_MODE_SGMII:
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@@ -814,6 +816,7 @@ static int phylink_parse_mode(struct phy
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switch (pl->link_config.interface) {
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case PHY_INTERFACE_MODE_SGMII:
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+ case PHY_INTERFACE_MODE_PSGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_QUSGMII:
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case PHY_INTERFACE_MODE_RGMII:
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--- a/include/linux/phy.h
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+++ b/include/linux/phy.h
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@@ -103,6 +103,7 @@ extern const int phy_10gbit_features_arr
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* @PHY_INTERFACE_MODE_XGMII: 10 gigabit media-independent interface
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* @PHY_INTERFACE_MODE_XLGMII:40 gigabit media-independent interface
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* @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax
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+ * @PHY_INTERFACE_MODE_PSGMII: Penta SGMII
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* @PHY_INTERFACE_MODE_QSGMII: Quad SGMII
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* @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII
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* @PHY_INTERFACE_MODE_100BASEX: 100 BaseX
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@@ -140,6 +141,7 @@ typedef enum {
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PHY_INTERFACE_MODE_XGMII,
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PHY_INTERFACE_MODE_XLGMII,
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PHY_INTERFACE_MODE_MOCA,
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+ PHY_INTERFACE_MODE_PSGMII,
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PHY_INTERFACE_MODE_QSGMII,
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PHY_INTERFACE_MODE_TRGMII,
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PHY_INTERFACE_MODE_100BASEX,
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@@ -247,6 +249,8 @@ static inline const char *phy_modes(phy_
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return "xlgmii";
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case PHY_INTERFACE_MODE_MOCA:
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return "moca";
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+ case PHY_INTERFACE_MODE_PSGMII:
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+ return "psgmii";
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case PHY_INTERFACE_MODE_QSGMII:
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return "qsgmii";
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case PHY_INTERFACE_MODE_TRGMII:
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