2023-05-21 21:02:17 +00:00
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From 5502ef9d40ab20b2ac683660d1565a7c4968bcc8 Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <openwrt@kresin.me>
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Date: Mon, 2 May 2016 18:50:00 +0000
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Subject: [PATCH] xrx200: add gphy clk src device tree binding
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Signed-off-by: Mathias Kresin <openwrt@kresin.me>
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---
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arch/mips/lantiq/xway/sysctrl.c | 16 ++++++++++++++++
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1 file changed, 16 insertions(+)
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2022-03-21 17:32:41 +00:00
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -440,6 +440,20 @@ static void clkdev_add_clkout(void)
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}
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}
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+static void set_phy_clock_source(struct device_node *np_cgu)
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+{
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+ u32 phy_clk_src, ifcc;
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+
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+ if (!np_cgu)
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+ return;
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+
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+ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
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+ return;
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+
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+ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
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+ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
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+}
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+
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/* bring up all register ranges that we need for basic system control */
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void __init ltq_soc_init(void)
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{
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@@ -605,4 +619,6 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
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}
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usb_set_clock();
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+
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+ set_phy_clock_source(np_cgu);
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}
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