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35 lines
1.2 KiB
Diff
35 lines
1.2 KiB
Diff
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From f2ca10b22ace3ce53b4e3f189bf1dd53a4482475 Mon Sep 17 00:00:00 2001
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From: INAGAKI Hiroshi <musashino.open@gmail.com>
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Date: Fri, 26 Apr 2024 23:53:58 +0900
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Subject: [PATCH 1/2] MIPS: pci-ar724x: clear power down of pll on AR934x
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Fix PCIe initialization on AR934x by clearing PLL_PWD bit in addition to
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PPL_RESET bit of AR724x.
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Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
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---
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -347,6 +347,8 @@
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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+#define AR934X_PLL_PCIE_CONFIG_PLL_PWD BIT(30)
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+
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#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
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#define QCA953X_PLL_CPU_CONFIG_REG 0x00
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--- a/arch/mips/pci/pci-ar724x.c
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+++ b/arch/mips/pci/pci-ar724x.c
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@@ -360,7 +360,8 @@ static void ar724x_pci_hw_init(struct ar
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} else {
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/* remove the reset of the PCIE PLL */
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ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
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+ ppl &= ~(AR934X_PLL_PCIE_CONFIG_PLL_PWD |
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+ AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET);
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ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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/* deassert bypass for the PCIE PLL */
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