mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 15:02:32 +00:00
47 lines
1.9 KiB
Diff
47 lines
1.9 KiB
Diff
|
From 8df9fefd1d04f6f97f6015d7347104f69e6ea580 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Baruch Siach <baruch.siach@siklu.com>
|
||
|
|
Date: Tue, 21 Jun 2022 11:54:52 +0300
|
||
|
|
Subject: [PATCH] PCI: dwc: Move GEN3_RELATED DBI definitions to common header
|
||
|
|
|
||
|
|
These are common dwc macros that will be used for other platforms.
|
||
|
|
|
||
|
|
Link: https://lore.kernel.org/r/1c2d5a7a139be81fa15f356b2380163dbdebdc09.1655799816.git.baruch@tkos.co.il
|
||
|
|
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
|
||
|
|
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
||
|
|
Reviewed-by: Rob Herring <robh@kernel.org>
|
||
|
|
---
|
||
|
|
drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
|
||
|
|
drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
|
||
|
|
2 files changed, 6 insertions(+), 6 deletions(-)
|
||
|
|
|
||
|
|
--- a/drivers/pci/controller/dwc/pcie-designware.h
|
||
|
|
+++ b/drivers/pci/controller/dwc/pcie-designware.h
|
||
|
|
@@ -74,6 +74,12 @@
|
||
|
|
#define PCIE_MSI_INTR0_MASK 0x82C
|
||
|
|
#define PCIE_MSI_INTR0_STATUS 0x830
|
||
|
|
|
||
|
|
+#define GEN3_RELATED_OFF 0x890
|
||
|
|
+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
|
||
|
|
+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
|
||
|
|
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
|
||
|
|
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
|
||
|
|
+
|
||
|
|
#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
|
||
|
|
#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
|
||
|
|
|
||
|
|
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
|
||
|
|
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
|
||
|
|
@@ -193,12 +193,6 @@
|
||
|
|
#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
|
||
|
|
#define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
|
||
|
|
|
||
|
|
-#define GEN3_RELATED_OFF 0x890
|
||
|
|
-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
|
||
|
|
-#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
|
||
|
|
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
|
||
|
|
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
|
||
|
|
-
|
||
|
|
#define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
|
||
|
|
#define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
|
||
|
|
#define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
|