2023-05-06 10:45:56 +00:00
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From 157ac9f52fd9b9a22cf12f7755a905fb34ef72f7 Mon Sep 17 00:00:00 2001
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2021-11-01 12:02:53 +00:00
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From: Gabor Juhos <j4g8y7@gmail.com>
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Date: Fri, 25 Dec 2020 08:02:47 +0100
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Subject: [PATCH] net: phy: define PSGMII PHY interface mode
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The PSGMII interface is similar to QSGMII. The main difference
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is that the PSGMII interface combines five SGMII lines into a
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single link while in QSGMII only four lines are combined.
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Similarly to the QSGMII, this interface mode might also needs
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special handling within the MAC driver.
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Add definitions for the PHY layer to allow to express this type
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of connection between the MAC and PHY.
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Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
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---
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Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
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2023-05-06 10:45:56 +00:00
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drivers/net/phy/phylink.c | 2 ++
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2021-11-01 12:02:53 +00:00
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include/linux/phy.h | 3 +++
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2023-05-06 10:45:56 +00:00
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3 files changed, 6 insertions(+)
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--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
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+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
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@@ -64,6 +64,7 @@ properties:
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- mii
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- gmii
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- sgmii
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+ - psgmii
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- qsgmii
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- tbi
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- rev-mii
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2024-02-07 08:17:50 +00:00
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--- a/drivers/net/phy/phy-core.c
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+++ b/drivers/net/phy/phy-core.c
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@@ -140,6 +140,8 @@ int phy_interface_num_ports(phy_interfac
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_QUSGMII:
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return 4;
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+ case PHY_INTERFACE_MODE_PSGMII:
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+ return 5;
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case PHY_INTERFACE_MODE_MAX:
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WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode");
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return 0;
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2021-11-01 12:02:53 +00:00
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--- a/drivers/net/phy/phylink.c
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+++ b/drivers/net/phy/phylink.c
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2023-08-26 01:19:18 +00:00
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@@ -371,6 +371,7 @@ void phylink_get_linkmodes(unsigned long
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2023-05-06 10:45:56 +00:00
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII:
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+ case PHY_INTERFACE_MODE_PSGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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2024-01-26 05:35:27 +00:00
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case PHY_INTERFACE_MODE_QUSGMII:
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2023-05-06 10:45:56 +00:00
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case PHY_INTERFACE_MODE_SGMII:
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2024-01-26 05:35:27 +00:00
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@@ -636,6 +637,7 @@ static int phylink_parse_mode(struct phy
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switch (pl->link_config.interface) {
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case PHY_INTERFACE_MODE_SGMII:
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+ case PHY_INTERFACE_MODE_PSGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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2024-01-26 05:35:27 +00:00
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case PHY_INTERFACE_MODE_QUSGMII:
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2021-11-01 12:02:53 +00:00
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phylink_set(pl->supported, 10baseT_Half);
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--- a/include/linux/phy.h
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+++ b/include/linux/phy.h
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2024-01-26 05:35:27 +00:00
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@@ -141,6 +141,7 @@ typedef enum {
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PHY_INTERFACE_MODE_XGMII,
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PHY_INTERFACE_MODE_XLGMII,
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PHY_INTERFACE_MODE_MOCA,
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+ PHY_INTERFACE_MODE_PSGMII,
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PHY_INTERFACE_MODE_QSGMII,
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PHY_INTERFACE_MODE_TRGMII,
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PHY_INTERFACE_MODE_100BASEX,
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2024-01-26 05:35:27 +00:00
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@@ -248,6 +249,8 @@ static inline const char *phy_modes(phy_
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2021-11-01 12:02:53 +00:00
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return "xlgmii";
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case PHY_INTERFACE_MODE_MOCA:
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return "moca";
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+ case PHY_INTERFACE_MODE_PSGMII:
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+ return "psgmii";
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case PHY_INTERFACE_MODE_QSGMII:
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return "qsgmii";
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case PHY_INTERFACE_MODE_TRGMII:
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