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43 lines
1.4 KiB
Diff
43 lines
1.4 KiB
Diff
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From 8c9e8b0a28225c46f2cca0a09a3a111bb043e874 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
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Date: Wed, 17 Jun 2020 12:50:41 +0200
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Subject: [PATCH 9/9] mips: bmips: add BCM6318 reset controller definitions
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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BCM6318 SoCs have a reset controller for certain components.
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Acked-by: Florian Fainelli <F.fainelli@gmail.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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include/dt-bindings/reset/bcm6318-reset.h | 20 ++++++++++++++++++++
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1 file changed, 20 insertions(+)
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create mode 100644 include/dt-bindings/reset/bcm6318-reset.h
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--- /dev/null
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+++ b/include/dt-bindings/reset/bcm6318-reset.h
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@@ -0,0 +1,20 @@
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+/* SPDX-License-Identifier: GPL-2.0+ */
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+
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+#ifndef __DT_BINDINGS_RESET_BCM6318_H
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+#define __DT_BINDINGS_RESET_BCM6318_H
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+
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+#define BCM6318_RST_SPI 0
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+#define BCM6318_RST_EPHY 1
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+#define BCM6318_RST_SAR 2
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+#define BCM6318_RST_ENETSW 3
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+#define BCM6318_RST_USBD 4
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+#define BCM6318_RST_USBH 5
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+#define BCM6318_RST_PCIE_CORE 6
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+#define BCM6318_RST_PCIE 7
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+#define BCM6318_RST_PCIE_EXT 8
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+#define BCM6318_RST_PCIE_HARD 9
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+#define BCM6318_RST_ADSL 10
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+#define BCM6318_RST_PHYMIPS 11
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+#define BCM6318_RST_HOSTMIPS 12
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+
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+#endif /* __DT_BINDINGS_RESET_BCM6318_H */
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