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68 lines
2.5 KiB
Diff
68 lines
2.5 KiB
Diff
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From f72e99ada020a81e3e4ef79c0a83ede7e9d6c7b1 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 16 Aug 2020 14:42:17 +0200
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Subject: [PATCH v2 446/447] mtd: spinand: gigadevice: Add QE Bit
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The following GigaDevice chips have the QE BIT in the feature flags, I
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checked the datasheets, but did not try this.
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* GD5F1GQ4xExxG
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* GD5F1GQ4xFxxG
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* GD5F1GQ4UAYIG
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* GD5F4GQ4UAYIG
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The Quad operations like 0xEB mention that the QE bit has to be set.
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Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA")
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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drivers/mtd/nand/spi/gigadevice.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -201,7 +201,7 @@ static const struct spinand_info gigadev
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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- 0,
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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SPINAND_INFO("GD5F2GQ4xA", 0xF2,
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@@ -210,7 +210,7 @@ static const struct spinand_info gigadev
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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- 0,
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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SPINAND_INFO("GD5F4GQ4xA", 0xF4,
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@@ -219,7 +219,7 @@ static const struct spinand_info gigadev
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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- 0,
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
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gd5fxgq4xa_ecc_get_status)),
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SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
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@@ -228,7 +228,7 @@ static const struct spinand_info gigadev
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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- 0,
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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gd5fxgq4uexxg_ecc_get_status)),
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SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148,
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@@ -237,7 +237,7 @@ static const struct spinand_info gigadev
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
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&write_cache_variants,
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&update_cache_variants),
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- 0,
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+ SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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gd5fxgq4ufxxg_ecc_get_status)),
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};
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