2022-05-16 21:40:32 +00:00
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From 77b0e8ded57e7fb5d742fb533d7a9bb3f3788513 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Wed, 13 Jan 2021 11:20:08 +0100
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Subject: [PATCH] drm/vc4: hdmi: Replace CSC_CTL hardcoded value by
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defines
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On BCM2711, the HDMI_CSC_CTL register value has been hardcoded to an
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opaque value. Let's replace it with properly defined values.
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Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 5 ++---
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drivers/gpu/drm/vc4/vc4_regs.h | 3 +++
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2 files changed, 5 insertions(+), 3 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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2022-05-18 14:32:03 +00:00
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@@ -786,9 +786,8 @@ static void vc5_hdmi_csc_setup(struct vc
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2022-05-16 21:40:32 +00:00
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const struct drm_display_mode *mode)
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{
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unsigned long flags;
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- u32 csc_ctl;
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-
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- csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
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+ u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
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+ VC5_MT_CP_CSC_CTL_MODE);
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spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -796,6 +796,9 @@ enum {
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# define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
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# define VC4_HD_CSC_CTL_ENABLE BIT(0)
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+# define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
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+# define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)
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+
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# define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
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/* HVS display list information. */
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