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67 lines
2.0 KiB
Diff
67 lines
2.0 KiB
Diff
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From b81ea0a64b01ae42e8b41d2a8b9a3fabffe97489 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Mon, 24 Apr 2023 09:38:29 +0200
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Subject: [PATCH 4/5] arm: Add support for the Broadcom Northstar SoCs
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The original Northstar is an ARM SoC series that comprise
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BCM4709x and BCM5301x and uses a dual-core Cortex A9, the
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global timer and a few other things.
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This series should not be confused with North Star Plus
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(NSP) which is partly supported by U-Boot already.
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The SoC is well supported by the Linux kernel and OpenWrt
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as it is used in many routers.
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Since we currently don't need any chip-specific quirks
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and can get the system up from just the device tree, a
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mach-* directory doesn't even need to be added, just
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some small Kconfig fragments.
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Cc: Rafał Miłecki <rafal@milecki.pl>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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arch/arm/Kconfig | 21 ++++++++++++++++++++-
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1 file changed, 20 insertions(+), 1 deletion(-)
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--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -357,7 +357,7 @@ config SYS_ARM_ARCH
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choice
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prompt "Select the ARM data write cache policy"
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- default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
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+ default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNS || RZA1
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default SYS_ARM_CACHE_WRITEBACK
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config SYS_ARM_CACHE_WRITEBACK
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@@ -670,6 +670,25 @@ config TARGET_BCMCYGNUS
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imply HASH_VERIFY
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imply NETDEVICES
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+config TARGET_BCMNS
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+ bool "Support Broadcom Northstar"
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+ select CPU_V7A
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+ select DM
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+ select DM_GPIO
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+ select DM_SERIAL
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+ select OF_CONTROL
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+ select TIMER
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+ select SYS_NS16550
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+ select ARM_GLOBAL_TIMER
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+ imply SYS_THUMB_BUILD
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+ imply MTD_RAW_NAND
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+ imply NAND_BRCMNAND
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+ imply NAND_BRCMNAND_IPROC
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+ help
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+ Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
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+ ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
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+ BCM5301x etc.
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+
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config TARGET_BCMNS2
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bool "Support Broadcom Northstar2"
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select ARM64
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