2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_ALIGNMENT_TRAP=y
|
|
|
|
|
# CONFIG_APQ_GCC_8084 is not set
|
|
|
|
|
# CONFIG_APQ_MMCC_8084 is not set
|
|
|
|
|
CONFIG_AR40XX_PHY=y
|
|
|
|
|
CONFIG_ARCH_CLOCKSOURCE_DATA=y
|
|
|
|
|
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
|
|
|
|
|
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
|
|
|
|
|
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
|
|
|
|
|
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
|
|
|
|
|
CONFIG_ARCH_HAS_KCOV=y
|
|
|
|
|
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
|
|
|
|
|
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
|
|
|
|
|
CONFIG_ARCH_HAS_SET_MEMORY=y
|
|
|
|
|
CONFIG_ARCH_HAS_SG_CHAIN=y
|
|
|
|
|
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
|
|
|
|
|
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
|
|
|
|
|
CONFIG_ARCH_HAS_TICK_BROADCAST=y
|
|
|
|
|
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
|
|
|
|
|
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
|
|
|
|
CONFIG_ARCH_IPQ40XX=y
|
|
|
|
|
# CONFIG_ARCH_MDM9615 is not set
|
|
|
|
|
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
|
|
|
|
|
# CONFIG_ARCH_MSM8960 is not set
|
|
|
|
|
# CONFIG_ARCH_MSM8974 is not set
|
|
|
|
|
# CONFIG_ARCH_MSM8X60 is not set
|
|
|
|
|
CONFIG_ARCH_MULTIPLATFORM=y
|
|
|
|
|
CONFIG_ARCH_MULTI_V6_V7=y
|
|
|
|
|
CONFIG_ARCH_MULTI_V7=y
|
|
|
|
|
CONFIG_ARCH_NR_GPIO=0
|
|
|
|
|
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
|
|
|
|
|
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
|
|
|
|
|
CONFIG_ARCH_QCOM=y
|
|
|
|
|
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
|
|
|
|
|
CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
|
|
|
|
|
CONFIG_ARCH_SUPPORTS_UPROBES=y
|
|
|
|
|
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
|
|
|
|
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
|
|
|
|
|
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
|
|
|
|
|
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
|
|
|
|
|
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
|
|
|
|
|
CONFIG_ARM=y
|
|
|
|
|
CONFIG_ARM_AMBA=y
|
|
|
|
|
CONFIG_ARM_APPENDED_DTB=y
|
|
|
|
|
CONFIG_ARM_ARCH_TIMER=y
|
|
|
|
|
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
|
|
|
|
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
|
|
|
|
|
CONFIG_ARM_CPUIDLE=y
|
|
|
|
|
CONFIG_ARM_CPU_SUSPEND=y
|
|
|
|
|
# CONFIG_ARM_CPU_TOPOLOGY is not set
|
ipq40xx: use neon crypto drivers
This adds the neon based implementations of AES & SHA256.
For AES, according to the kernel config help:
Use a faster and more secure NEON based implementation of AES in CBC,
CTR and XTS modes.
Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
and for XTS mode encryption, CBC and XTS mode decryption speedup is
around 25%. (CBC encryption speed is not affected by this driver.)
This implementation does not rely on any lookup tables so it is
believed to be invulnerable to cache timing attacks.
...
The observed speedups on ipq40xx are more modest: speedup is around 20%
for CTR mode and for XTS mode encryption, CBC and XTS mode decryption
speedup is around 10%. Measurements were made using tcrypt, with
1024-bytes blocks for CTR & CBC, and 4096-bytes for XTS.
The aes-neon-bs driver uses a fallback for CBC encryption; that fallback
could be either the generic driver written in C, or the scalar arm-asm
one. Even though aes-arm is 1.9% slower, it is more resilient to timing
attacks (the reason for being slower), so it is being included here.
The neon sha256 module increases performance over the generic module by
33%.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
[Enable only ciphers for now, reorder patch in series to help bisect
as new symbols could lead to build failures, 5.4]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2020-02-21 18:44:39 +00:00
|
|
|
CONFIG_ARM_CRYPTO=y
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_ARM_GIC=y
|
|
|
|
|
CONFIG_ARM_HAS_SG_CHAIN=y
|
|
|
|
|
CONFIG_ARM_L1_CACHE_SHIFT=6
|
|
|
|
|
CONFIG_ARM_L1_CACHE_SHIFT_6=y
|
|
|
|
|
# CONFIG_ARM_LPAE is not set
|
|
|
|
|
CONFIG_ARM_PATCH_IDIV=y
|
|
|
|
|
CONFIG_ARM_PATCH_PHYS_VIRT=y
|
|
|
|
|
# CONFIG_ARM_SMMU is not set
|
|
|
|
|
# CONFIG_ARM_SP805_WATCHDOG is not set
|
|
|
|
|
CONFIG_ARM_THUMB=y
|
|
|
|
|
# CONFIG_ARM_THUMBEE is not set
|
|
|
|
|
CONFIG_ARM_UNWIND=y
|
|
|
|
|
CONFIG_ARM_VIRT_EXT=y
|
|
|
|
|
CONFIG_AT803X_PHY=y
|
|
|
|
|
CONFIG_AUTO_ZRELADDR=y
|
|
|
|
|
CONFIG_BLK_DEV_LOOP=y
|
|
|
|
|
CONFIG_BLK_MQ_PCI=y
|
|
|
|
|
CONFIG_BOUNCE=y
|
|
|
|
|
# CONFIG_CACHE_L2X0 is not set
|
|
|
|
|
CONFIG_CLKDEV_LOOKUP=y
|
|
|
|
|
CONFIG_CLKSRC_QCOM=y
|
|
|
|
|
CONFIG_CLONE_BACKWARDS=y
|
|
|
|
|
CONFIG_COMMON_CLK=y
|
|
|
|
|
CONFIG_COMMON_CLK_QCOM=y
|
|
|
|
|
CONFIG_CPUFREQ_DT=y
|
|
|
|
|
CONFIG_CPUFREQ_DT_PLATDEV=y
|
|
|
|
|
CONFIG_CPU_32v6K=y
|
|
|
|
|
CONFIG_CPU_32v7=y
|
|
|
|
|
CONFIG_CPU_ABRT_EV7=y
|
|
|
|
|
# CONFIG_CPU_BIG_ENDIAN is not set
|
|
|
|
|
# CONFIG_CPU_BPREDICT_DISABLE is not set
|
|
|
|
|
CONFIG_CPU_CACHE_V7=y
|
|
|
|
|
CONFIG_CPU_CACHE_VIPT=y
|
|
|
|
|
CONFIG_CPU_COPY_V6=y
|
|
|
|
|
CONFIG_CPU_CP15=y
|
|
|
|
|
CONFIG_CPU_CP15_MMU=y
|
|
|
|
|
CONFIG_CPU_FREQ=y
|
|
|
|
|
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
|
|
|
|
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
|
|
|
|
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
|
|
|
|
CONFIG_CPU_FREQ_GOV_COMMON=y
|
|
|
|
|
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
|
|
|
|
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
|
|
|
|
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
|
|
|
|
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
|
|
|
|
|
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
|
|
|
|
CONFIG_CPU_FREQ_STAT=y
|
|
|
|
|
CONFIG_CPU_HAS_ASID=y
|
|
|
|
|
# CONFIG_CPU_ICACHE_DISABLE is not set
|
|
|
|
|
CONFIG_CPU_IDLE=y
|
|
|
|
|
CONFIG_CPU_IDLE_GOV_LADDER=y
|
|
|
|
|
CONFIG_CPU_IDLE_GOV_MENU=y
|
|
|
|
|
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
|
|
|
|
|
CONFIG_CPU_PABRT_V7=y
|
|
|
|
|
CONFIG_CPU_PM=y
|
|
|
|
|
CONFIG_CPU_RMAP=y
|
|
|
|
|
CONFIG_CPU_SPECTRE=y
|
|
|
|
|
CONFIG_CPU_THERMAL=y
|
|
|
|
|
CONFIG_CPU_THUMB_CAPABLE=y
|
|
|
|
|
CONFIG_CPU_TLB_V7=y
|
|
|
|
|
CONFIG_CPU_V7=y
|
|
|
|
|
CONFIG_CRC16=y
|
|
|
|
|
# CONFIG_CRC32_SARWATE is not set
|
|
|
|
|
CONFIG_CRC32_SLICEBY8=y
|
|
|
|
|
CONFIG_CRYPTO_ACOMP2=y
|
|
|
|
|
CONFIG_CRYPTO_AEAD=y
|
|
|
|
|
CONFIG_CRYPTO_AEAD2=y
|
ipq40xx: use neon crypto drivers
This adds the neon based implementations of AES & SHA256.
For AES, according to the kernel config help:
Use a faster and more secure NEON based implementation of AES in CBC,
CTR and XTS modes.
Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
and for XTS mode encryption, CBC and XTS mode decryption speedup is
around 25%. (CBC encryption speed is not affected by this driver.)
This implementation does not rely on any lookup tables so it is
believed to be invulnerable to cache timing attacks.
...
The observed speedups on ipq40xx are more modest: speedup is around 20%
for CTR mode and for XTS mode encryption, CBC and XTS mode decryption
speedup is around 10%. Measurements were made using tcrypt, with
1024-bytes blocks for CTR & CBC, and 4096-bytes for XTS.
The aes-neon-bs driver uses a fallback for CBC encryption; that fallback
could be either the generic driver written in C, or the scalar arm-asm
one. Even though aes-arm is 1.9% slower, it is more resilient to timing
attacks (the reason for being slower), so it is being included here.
The neon sha256 module increases performance over the generic module by
33%.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
[Enable only ciphers for now, reorder patch in series to help bisect
as new symbols could lead to build failures, 5.4]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2020-02-21 18:44:39 +00:00
|
|
|
CONFIG_CRYPTO_AES_ARM=y
|
|
|
|
|
CONFIG_CRYPTO_AES_ARM_BS=y
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_CRYPTO_CBC=y
|
|
|
|
|
CONFIG_CRYPTO_CTR=y
|
|
|
|
|
CONFIG_CRYPTO_DEFLATE=y
|
|
|
|
|
CONFIG_CRYPTO_DES=y
|
|
|
|
|
CONFIG_CRYPTO_DEV_QCE=y
|
ipq40xx: use neon crypto drivers
This adds the neon based implementations of AES & SHA256.
For AES, according to the kernel config help:
Use a faster and more secure NEON based implementation of AES in CBC,
CTR and XTS modes.
Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
and for XTS mode encryption, CBC and XTS mode decryption speedup is
around 25%. (CBC encryption speed is not affected by this driver.)
This implementation does not rely on any lookup tables so it is
believed to be invulnerable to cache timing attacks.
...
The observed speedups on ipq40xx are more modest: speedup is around 20%
for CTR mode and for XTS mode encryption, CBC and XTS mode decryption
speedup is around 10%. Measurements were made using tcrypt, with
1024-bytes blocks for CTR & CBC, and 4096-bytes for XTS.
The aes-neon-bs driver uses a fallback for CBC encryption; that fallback
could be either the generic driver written in C, or the scalar arm-asm
one. Even though aes-arm is 1.9% slower, it is more resilient to timing
attacks (the reason for being slower), so it is being included here.
The neon sha256 module increases performance over the generic module by
33%.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
[Enable only ciphers for now, reorder patch in series to help bisect
as new symbols could lead to build failures, 5.4]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2020-02-21 18:44:39 +00:00
|
|
|
# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
|
|
|
|
|
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
|
|
|
|
|
CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
|
|
|
|
|
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
|
2018-12-19 12:57:19 +00:00
|
|
|
CONFIG_CRYPTO_DEV_QCOM_RNG=y
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_CRYPTO_DRBG=y
|
|
|
|
|
CONFIG_CRYPTO_DRBG_HMAC=y
|
|
|
|
|
CONFIG_CRYPTO_DRBG_MENU=y
|
|
|
|
|
CONFIG_CRYPTO_ECB=y
|
|
|
|
|
CONFIG_CRYPTO_GF128MUL=y
|
ipq40xx: use neon crypto drivers
This adds the neon based implementations of AES & SHA256.
For AES, according to the kernel config help:
Use a faster and more secure NEON based implementation of AES in CBC,
CTR and XTS modes.
Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
and for XTS mode encryption, CBC and XTS mode decryption speedup is
around 25%. (CBC encryption speed is not affected by this driver.)
This implementation does not rely on any lookup tables so it is
believed to be invulnerable to cache timing attacks.
...
The observed speedups on ipq40xx are more modest: speedup is around 20%
for CTR mode and for XTS mode encryption, CBC and XTS mode decryption
speedup is around 10%. Measurements were made using tcrypt, with
1024-bytes blocks for CTR & CBC, and 4096-bytes for XTS.
The aes-neon-bs driver uses a fallback for CBC encryption; that fallback
could be either the generic driver written in C, or the scalar arm-asm
one. Even though aes-arm is 1.9% slower, it is more resilient to timing
attacks (the reason for being slower), so it is being included here.
The neon sha256 module increases performance over the generic module by
33%.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
[Enable only ciphers for now, reorder patch in series to help bisect
as new symbols could lead to build failures, 5.4]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2020-02-21 18:44:39 +00:00
|
|
|
# CONFIG_CRYPTO_GHASH_ARM_CE is not set
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_CRYPTO_HASH=y
|
|
|
|
|
CONFIG_CRYPTO_HASH2=y
|
|
|
|
|
CONFIG_CRYPTO_HMAC=y
|
|
|
|
|
CONFIG_CRYPTO_HW=y
|
|
|
|
|
CONFIG_CRYPTO_JITTERENTROPY=y
|
|
|
|
|
CONFIG_CRYPTO_LZO=y
|
|
|
|
|
CONFIG_CRYPTO_MANAGER=y
|
|
|
|
|
CONFIG_CRYPTO_MANAGER2=y
|
|
|
|
|
CONFIG_CRYPTO_NULL=y
|
|
|
|
|
CONFIG_CRYPTO_NULL2=y
|
|
|
|
|
CONFIG_CRYPTO_RNG=y
|
|
|
|
|
CONFIG_CRYPTO_RNG2=y
|
|
|
|
|
CONFIG_CRYPTO_RNG_DEFAULT=y
|
|
|
|
|
CONFIG_CRYPTO_SEQIV=y
|
ipq40xx: use neon crypto drivers
This adds the neon based implementations of AES & SHA256.
For AES, according to the kernel config help:
Use a faster and more secure NEON based implementation of AES in CBC,
CTR and XTS modes.
Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
and for XTS mode encryption, CBC and XTS mode decryption speedup is
around 25%. (CBC encryption speed is not affected by this driver.)
This implementation does not rely on any lookup tables so it is
believed to be invulnerable to cache timing attacks.
...
The observed speedups on ipq40xx are more modest: speedup is around 20%
for CTR mode and for XTS mode encryption, CBC and XTS mode decryption
speedup is around 10%. Measurements were made using tcrypt, with
1024-bytes blocks for CTR & CBC, and 4096-bytes for XTS.
The aes-neon-bs driver uses a fallback for CBC encryption; that fallback
could be either the generic driver written in C, or the scalar arm-asm
one. Even though aes-arm is 1.9% slower, it is more resilient to timing
attacks (the reason for being slower), so it is being included here.
The neon sha256 module increases performance over the generic module by
33%.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
[Enable only ciphers for now, reorder patch in series to help bisect
as new symbols could lead to build failures, 5.4]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2020-02-21 18:44:39 +00:00
|
|
|
# CONFIG_CRYPTO_SHA1_ARM_CE is not set
|
|
|
|
|
# CONFIG_CRYPTO_SHA1_ARM_NEON is not set
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_CRYPTO_SHA256=y
|
ipq40xx: use neon crypto drivers
This adds the neon based implementations of AES & SHA256.
For AES, according to the kernel config help:
Use a faster and more secure NEON based implementation of AES in CBC,
CTR and XTS modes.
Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
and for XTS mode encryption, CBC and XTS mode decryption speedup is
around 25%. (CBC encryption speed is not affected by this driver.)
This implementation does not rely on any lookup tables so it is
believed to be invulnerable to cache timing attacks.
...
The observed speedups on ipq40xx are more modest: speedup is around 20%
for CTR mode and for XTS mode encryption, CBC and XTS mode decryption
speedup is around 10%. Measurements were made using tcrypt, with
1024-bytes blocks for CTR & CBC, and 4096-bytes for XTS.
The aes-neon-bs driver uses a fallback for CBC encryption; that fallback
could be either the generic driver written in C, or the scalar arm-asm
one. Even though aes-arm is 1.9% slower, it is more resilient to timing
attacks (the reason for being slower), so it is being included here.
The neon sha256 module increases performance over the generic module by
33%.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
[Enable only ciphers for now, reorder patch in series to help bisect
as new symbols could lead to build failures, 5.4]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2020-02-21 18:44:39 +00:00
|
|
|
CONFIG_CRYPTO_SHA256_ARM=y
|
|
|
|
|
CONFIG_CRYPTO_SIMD=y
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_CRYPTO_WORKQUEUE=y
|
|
|
|
|
CONFIG_CRYPTO_XTS=y
|
|
|
|
|
CONFIG_DCACHE_WORD_ACCESS=y
|
|
|
|
|
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
|
|
|
|
|
# CONFIG_DEBUG_USER is not set
|
|
|
|
|
CONFIG_DMADEVICES=y
|
|
|
|
|
CONFIG_DMA_ENGINE=y
|
|
|
|
|
CONFIG_DMA_OF=y
|
|
|
|
|
CONFIG_DMA_SHARED_BUFFER=y
|
|
|
|
|
CONFIG_DMA_VIRTUAL_CHANNELS=y
|
|
|
|
|
CONFIG_DTC=y
|
|
|
|
|
CONFIG_DT_IDLE_STATES=y
|
|
|
|
|
CONFIG_DYNAMIC_DEBUG=y
|
|
|
|
|
CONFIG_EDAC_ATOMIC_SCRUB=y
|
|
|
|
|
CONFIG_EDAC_SUPPORT=y
|
|
|
|
|
CONFIG_EEPROM_AT24=y
|
|
|
|
|
CONFIG_ESSEDMA=y
|
|
|
|
|
CONFIG_EXTCON=y
|
|
|
|
|
CONFIG_FIXED_PHY=y
|
|
|
|
|
CONFIG_FIX_EARLYCON_MEM=y
|
|
|
|
|
CONFIG_GENERIC_ALLOCATOR=y
|
|
|
|
|
CONFIG_GENERIC_BUG=y
|
|
|
|
|
CONFIG_GENERIC_CLOCKEVENTS=y
|
|
|
|
|
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
|
|
|
|
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
|
|
|
|
CONFIG_GENERIC_EARLY_IOREMAP=y
|
|
|
|
|
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
|
|
|
|
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
|
|
|
|
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
|
|
|
|
|
CONFIG_GENERIC_IRQ_SHOW=y
|
|
|
|
|
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
|
|
|
|
CONFIG_GENERIC_MSI_IRQ=y
|
|
|
|
|
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
|
|
|
|
CONFIG_GENERIC_PCI_IOMAP=y
|
|
|
|
|
CONFIG_GENERIC_PHY=y
|
|
|
|
|
CONFIG_GENERIC_PINCONF=y
|
|
|
|
|
CONFIG_GENERIC_PINCTRL_GROUPS=y
|
|
|
|
|
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
|
|
|
|
|
CONFIG_GENERIC_SCHED_CLOCK=y
|
|
|
|
|
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
|
|
|
|
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
|
|
|
|
CONFIG_GENERIC_STRNLEN_USER=y
|
|
|
|
|
CONFIG_GENERIC_TIME_VSYSCALL=y
|
|
|
|
|
CONFIG_GPIOLIB=y
|
|
|
|
|
CONFIG_GPIOLIB_IRQCHIP=y
|
|
|
|
|
CONFIG_GPIO_74X164=y
|
|
|
|
|
CONFIG_GPIO_SYSFS=y
|
|
|
|
|
CONFIG_GPIO_WATCHDOG=y
|
|
|
|
|
# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
|
|
|
|
|
CONFIG_HANDLE_DOMAIN_IRQ=y
|
|
|
|
|
CONFIG_HARDEN_BRANCH_PREDICTOR=y
|
|
|
|
|
CONFIG_HARDIRQS_SW_RESEND=y
|
|
|
|
|
CONFIG_HAS_DMA=y
|
|
|
|
|
CONFIG_HAS_IOMEM=y
|
|
|
|
|
CONFIG_HAS_IOPORT_MAP=y
|
|
|
|
|
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
|
|
|
|
|
CONFIG_HAVE_ARCH_BITREVERSE=y
|
|
|
|
|
CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
|
|
|
|
CONFIG_HAVE_ARCH_KGDB=y
|
|
|
|
|
CONFIG_HAVE_ARCH_PFN_VALID=y
|
|
|
|
|
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
|
|
|
|
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
|
|
|
|
|
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
|
|
|
|
CONFIG_HAVE_ARM_ARCH_TIMER=y
|
|
|
|
|
CONFIG_HAVE_ARM_SMCCC=y
|
|
|
|
|
CONFIG_HAVE_CLK=y
|
|
|
|
|
CONFIG_HAVE_CLK_PREPARE=y
|
|
|
|
|
CONFIG_HAVE_CONTEXT_TRACKING=y
|
|
|
|
|
CONFIG_HAVE_C_RECORDMCOUNT=y
|
|
|
|
|
CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
|
|
|
|
CONFIG_HAVE_DMA_CONTIGUOUS=y
|
|
|
|
|
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
|
|
|
|
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
|
|
|
|
|
CONFIG_HAVE_EBPF_JIT=y
|
|
|
|
|
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
|
|
|
|
|
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
|
|
|
|
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
|
|
|
|
CONFIG_HAVE_FUNCTION_TRACER=y
|
|
|
|
|
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
|
|
|
|
CONFIG_HAVE_IDE=y
|
|
|
|
|
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
|
|
|
|
CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
|
|
|
|
|
CONFIG_HAVE_MEMBLOCK=y
|
|
|
|
|
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
|
|
|
|
|
CONFIG_HAVE_NET_DSA=y
|
|
|
|
|
CONFIG_HAVE_OPROFILE=y
|
|
|
|
|
CONFIG_HAVE_OPTPROBES=y
|
|
|
|
|
CONFIG_HAVE_PERF_EVENTS=y
|
|
|
|
|
CONFIG_HAVE_PERF_REGS=y
|
|
|
|
|
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
|
|
|
|
|
CONFIG_HAVE_PROC_CPU=y
|
|
|
|
|
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
|
|
|
|
|
CONFIG_HAVE_RSEQ=y
|
|
|
|
|
CONFIG_HAVE_SMP=y
|
|
|
|
|
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
|
|
|
|
CONFIG_HAVE_UID16=y
|
|
|
|
|
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
|
|
|
|
CONFIG_HIGHMEM=y
|
|
|
|
|
# CONFIG_HIGHPTE is not set
|
|
|
|
|
CONFIG_HWSPINLOCK=y
|
|
|
|
|
CONFIG_HWSPINLOCK_QCOM=y
|
|
|
|
|
CONFIG_HW_RANDOM=y
|
|
|
|
|
CONFIG_HZ_FIXED=0
|
|
|
|
|
CONFIG_I2C=y
|
|
|
|
|
CONFIG_I2C_BOARDINFO=y
|
|
|
|
|
CONFIG_I2C_CHARDEV=y
|
|
|
|
|
CONFIG_I2C_HELPER_AUTO=y
|
|
|
|
|
CONFIG_I2C_QUP=y
|
|
|
|
|
CONFIG_INITRAMFS_SOURCE=""
|
|
|
|
|
# CONFIG_IOMMU_DEBUGFS is not set
|
|
|
|
|
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
|
|
|
|
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
|
|
|
|
|
CONFIG_IOMMU_SUPPORT=y
|
|
|
|
|
CONFIG_IPQ_GCC_4019=y
|
|
|
|
|
# CONFIG_IPQ_GCC_806X is not set
|
|
|
|
|
# CONFIG_IPQ_GCC_8074 is not set
|
|
|
|
|
# CONFIG_IPQ_LCC_806X is not set
|
|
|
|
|
CONFIG_IRQCHIP=y
|
|
|
|
|
CONFIG_IRQ_DOMAIN=y
|
|
|
|
|
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
|
|
|
|
CONFIG_IRQ_FORCED_THREADING=y
|
|
|
|
|
CONFIG_IRQ_WORK=y
|
2020-04-07 21:43:34 +00:00
|
|
|
CONFIG_LEDS_LP5523=y
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_LEDS_LP5562=y
|
|
|
|
|
CONFIG_LEDS_LP55XX_COMMON=y
|
|
|
|
|
CONFIG_LIBFDT=y
|
|
|
|
|
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
|
|
|
|
CONFIG_LOCK_SPIN_ON_OWNER=y
|
|
|
|
|
CONFIG_LZO_COMPRESS=y
|
|
|
|
|
CONFIG_LZO_DECOMPRESS=y
|
|
|
|
|
CONFIG_MDIO_BITBANG=y
|
|
|
|
|
CONFIG_MDIO_BUS=y
|
|
|
|
|
CONFIG_MDIO_DEVICE=y
|
|
|
|
|
CONFIG_MDIO_GPIO=y
|
|
|
|
|
CONFIG_MDIO_IPQ40XX=y
|
|
|
|
|
# CONFIG_MDM_GCC_9615 is not set
|
|
|
|
|
# CONFIG_MDM_LCC_9615 is not set
|
|
|
|
|
CONFIG_MEMFD_CREATE=y
|
|
|
|
|
# CONFIG_MFD_QCOM_RPM is not set
|
|
|
|
|
# CONFIG_MFD_SPMI_PMIC is not set
|
|
|
|
|
CONFIG_MFD_SYSCON=y
|
|
|
|
|
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
|
|
|
|
|
CONFIG_MIGHT_HAVE_PCI=y
|
|
|
|
|
CONFIG_MIGRATION=y
|
2020-03-08 16:21:44 +00:00
|
|
|
CONFIG_MMC=y
|
|
|
|
|
CONFIG_MMC_BLOCK=y
|
|
|
|
|
CONFIG_MMC_SDHCI=y
|
|
|
|
|
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
|
|
|
|
|
CONFIG_MMC_SDHCI_MSM=y
|
|
|
|
|
# CONFIG_MMC_SDHCI_PCI is not set
|
|
|
|
|
CONFIG_MMC_SDHCI_PLTFM=y
|
|
|
|
|
# CONFIG_MMC_TIFM_SD is not set
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_MODULES_USE_ELF_REL=y
|
|
|
|
|
# CONFIG_MSM_GCC_8660 is not set
|
|
|
|
|
# CONFIG_MSM_GCC_8916 is not set
|
|
|
|
|
# CONFIG_MSM_GCC_8960 is not set
|
|
|
|
|
# CONFIG_MSM_GCC_8974 is not set
|
|
|
|
|
# CONFIG_MSM_GCC_8994 is not set
|
|
|
|
|
# CONFIG_MSM_GCC_8996 is not set
|
|
|
|
|
# CONFIG_MSM_GCC_8998 is not set
|
|
|
|
|
# CONFIG_MSM_LCC_8960 is not set
|
|
|
|
|
# CONFIG_MSM_MMCC_8960 is not set
|
|
|
|
|
# CONFIG_MSM_MMCC_8974 is not set
|
|
|
|
|
# CONFIG_MSM_MMCC_8996 is not set
|
|
|
|
|
CONFIG_MTD_CMDLINE_PARTS=y
|
|
|
|
|
CONFIG_MTD_M25P80=y
|
|
|
|
|
CONFIG_MTD_NAND=y
|
2018-12-16 22:10:06 +00:00
|
|
|
CONFIG_MTD_NAND_CORE=y
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_MTD_NAND_ECC=y
|
|
|
|
|
CONFIG_MTD_NAND_QCOM=y
|
2018-12-16 22:10:06 +00:00
|
|
|
CONFIG_MTD_SPI_NAND=y
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_MTD_SPI_NOR=y
|
|
|
|
|
CONFIG_MTD_SPLIT_FIRMWARE=y
|
|
|
|
|
CONFIG_MTD_SPLIT_FIT_FW=y
|
ipq40xx: Add support for D-Link DAP-2610
Specifications
==============
- SOC: IPQ4018
- RAM: DDR3 256MB
- Flash: SPI NOR 16MB
- WiFi:
- 2.4GHz: IPQ4018, 2x2, front end SKY85303-11
- 5GHz: IPQ4018, 2x2, front end SKY85717-21
- Ethernet: 1x 10/100/1000Mbps, POE 802.3af
- PHY: QCA8072
- UART: GND, blocked, 3.3V, RX, TX / 115200 8N1
- LED: 1x red / green
- Button: 1x reset / factory default
- U-Boot bootloader with tftp and "emergency web server" accessible
using serial port.
Installation
============
Flash factory image from D-Link web UI. Constraints in the D-Link web UI
makes the factory image unnecessarily large. Flash again using
sysupgrade from inside OpenWrt to reclaim some flash space.
Return to stock D-Link firmware
===============================
Partition layout is preserved, and it is possible to return to the stock
firmware simply by downloading it from D-Link and writing it to the
firmware partition.
# mtd -r write dap2610-firmware.bin firmware
Quirks
======
To be flashable from the D-Link http server, the firmware must be larger
then 6MB, and the size in the firmware header must match the actual file
size. Also, the boot loader verifies the checksum of the firmware before
each boot, thus the jffs2 must be after the checksum covered part. This
is solved in the factory image by having the rootfs at the very end of
the image (without pad-rootfs).
The sysupgrade image which does not have to be flashable from the D-Link
web UI may be smaller, and the checksum in the firmware header only
covers the kernel part of the image.
Signed-off-by: Fredrik Olofsson <fredrik.olofsson@anyfinetworks.com>
[added WRGG Variables to DEVICE_VARS, squashed spi pinconf/mux,
added emd1's gmac0 config,fix dtc warnings]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2019-09-10 09:25:53 +00:00
|
|
|
CONFIG_MTD_SPLIT_WRGG_FW=y
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_MTD_UBI=y
|
|
|
|
|
CONFIG_MTD_UBI_BEB_LIMIT=20
|
|
|
|
|
CONFIG_MTD_UBI_BLOCK=y
|
|
|
|
|
# CONFIG_MTD_UBI_FASTMAP is not set
|
|
|
|
|
# CONFIG_MTD_UBI_GLUEBI is not set
|
|
|
|
|
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
|
|
|
|
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
|
|
|
|
CONFIG_NEED_DMA_MAP_STATE=y
|
|
|
|
|
CONFIG_NEON=y
|
|
|
|
|
CONFIG_NET_DSA=y
|
|
|
|
|
CONFIG_NET_DSA_QCA8K=y
|
|
|
|
|
CONFIG_NET_DSA_TAG_QCA=y
|
|
|
|
|
CONFIG_NET_FLOW_LIMIT=y
|
|
|
|
|
CONFIG_NET_PTP_CLASSIFY=y
|
|
|
|
|
CONFIG_NET_SWITCHDEV=y
|
|
|
|
|
CONFIG_NLS=y
|
|
|
|
|
CONFIG_NO_BOOTMEM=y
|
|
|
|
|
CONFIG_NO_HZ=y
|
|
|
|
|
CONFIG_NO_HZ_COMMON=y
|
|
|
|
|
CONFIG_NO_HZ_IDLE=y
|
|
|
|
|
CONFIG_NR_CPUS=4
|
|
|
|
|
CONFIG_NVMEM=y
|
|
|
|
|
CONFIG_OF=y
|
|
|
|
|
CONFIG_OF_ADDRESS=y
|
|
|
|
|
CONFIG_OF_EARLY_FLATTREE=y
|
|
|
|
|
CONFIG_OF_FLATTREE=y
|
|
|
|
|
CONFIG_OF_GPIO=y
|
|
|
|
|
CONFIG_OF_IRQ=y
|
|
|
|
|
CONFIG_OF_KOBJ=y
|
|
|
|
|
CONFIG_OF_MDIO=y
|
|
|
|
|
CONFIG_OF_NET=y
|
|
|
|
|
CONFIG_OF_RESERVED_MEM=y
|
|
|
|
|
CONFIG_OLD_SIGACTION=y
|
|
|
|
|
CONFIG_OLD_SIGSUSPEND3=y
|
|
|
|
|
CONFIG_OPTEE=y
|
|
|
|
|
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
|
|
|
|
|
CONFIG_PADATA=y
|
|
|
|
|
CONFIG_PAGE_OFFSET=0xC0000000
|
|
|
|
|
CONFIG_PCI=y
|
|
|
|
|
CONFIG_PCIEAER=y
|
|
|
|
|
CONFIG_PCIEPORTBUS=y
|
|
|
|
|
CONFIG_PCIE_DW=y
|
|
|
|
|
CONFIG_PCIE_DW_HOST=y
|
|
|
|
|
CONFIG_PCIE_QCOM=y
|
|
|
|
|
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
|
|
|
|
|
CONFIG_PCI_DOMAINS=y
|
|
|
|
|
CONFIG_PCI_DOMAINS_GENERIC=y
|
|
|
|
|
CONFIG_PCI_MSI=y
|
|
|
|
|
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
|
|
|
|
CONFIG_PERF_USE_VMALLOC=y
|
|
|
|
|
CONFIG_PGTABLE_LEVELS=2
|
|
|
|
|
CONFIG_PHYLIB=y
|
|
|
|
|
CONFIG_PHYLINK=y
|
|
|
|
|
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
|
|
|
|
|
CONFIG_PHY_QCOM_IPQ4019_USB=y
|
|
|
|
|
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
|
|
|
|
|
# CONFIG_PHY_QCOM_QMP is not set
|
|
|
|
|
# CONFIG_PHY_QCOM_QUSB2 is not set
|
|
|
|
|
# CONFIG_PHY_QCOM_UFS is not set
|
|
|
|
|
CONFIG_PINCTRL=y
|
|
|
|
|
# CONFIG_PINCTRL_APQ8064 is not set
|
|
|
|
|
# CONFIG_PINCTRL_APQ8084 is not set
|
|
|
|
|
CONFIG_PINCTRL_IPQ4019=y
|
|
|
|
|
# CONFIG_PINCTRL_IPQ8064 is not set
|
|
|
|
|
# CONFIG_PINCTRL_IPQ8074 is not set
|
|
|
|
|
# CONFIG_PINCTRL_MDM9615 is not set
|
|
|
|
|
CONFIG_PINCTRL_MSM=y
|
|
|
|
|
# CONFIG_PINCTRL_MSM8660 is not set
|
|
|
|
|
# CONFIG_PINCTRL_MSM8916 is not set
|
|
|
|
|
# CONFIG_PINCTRL_MSM8960 is not set
|
|
|
|
|
# CONFIG_PINCTRL_MSM8994 is not set
|
|
|
|
|
# CONFIG_PINCTRL_MSM8996 is not set
|
|
|
|
|
# CONFIG_PINCTRL_MSM8998 is not set
|
|
|
|
|
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
|
|
|
|
|
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
|
|
|
|
|
# CONFIG_PINCTRL_SDM845 is not set
|
|
|
|
|
CONFIG_PM_OPP=y
|
|
|
|
|
CONFIG_POWER_RESET=y
|
|
|
|
|
CONFIG_POWER_RESET_MSM=y
|
|
|
|
|
CONFIG_POWER_SUPPLY=y
|
|
|
|
|
CONFIG_PPS=y
|
|
|
|
|
CONFIG_PRINTK_TIME=y
|
|
|
|
|
CONFIG_PTP_1588_CLOCK=y
|
|
|
|
|
CONFIG_QCOM_A53PLL=y
|
|
|
|
|
CONFIG_QCOM_BAM_DMA=y
|
|
|
|
|
# CONFIG_QCOM_COMMAND_DB is not set
|
|
|
|
|
# CONFIG_QCOM_EBI2 is not set
|
|
|
|
|
# CONFIG_QCOM_GENI_SE is not set
|
|
|
|
|
# CONFIG_QCOM_GSBI is not set
|
|
|
|
|
# CONFIG_QCOM_IOMMU is not set
|
|
|
|
|
# CONFIG_QCOM_LLCC is not set
|
|
|
|
|
# CONFIG_QCOM_PDC is not set
|
|
|
|
|
CONFIG_QCOM_PM=y
|
|
|
|
|
CONFIG_QCOM_QFPROM=y
|
|
|
|
|
# CONFIG_QCOM_RMTFS_MEM is not set
|
|
|
|
|
CONFIG_QCOM_SCM=y
|
|
|
|
|
CONFIG_QCOM_SCM_32=y
|
|
|
|
|
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
|
|
|
|
|
CONFIG_QCOM_SMEM=y
|
|
|
|
|
# CONFIG_QCOM_SMSM is not set
|
|
|
|
|
CONFIG_QCOM_TCSR=y
|
|
|
|
|
# CONFIG_QCOM_TSENS is not set
|
|
|
|
|
CONFIG_QCOM_WDT=y
|
|
|
|
|
# CONFIG_QRTR is not set
|
|
|
|
|
CONFIG_RAS=y
|
|
|
|
|
CONFIG_RATIONAL=y
|
|
|
|
|
CONFIG_RCU_CPU_STALL_TIMEOUT=21
|
|
|
|
|
CONFIG_RCU_NEED_SEGCBLIST=y
|
|
|
|
|
CONFIG_RCU_STALL_COMMON=y
|
|
|
|
|
CONFIG_REFCOUNT_FULL=y
|
|
|
|
|
CONFIG_REGMAP=y
|
|
|
|
|
CONFIG_REGMAP_I2C=y
|
|
|
|
|
CONFIG_REGMAP_MMIO=y
|
|
|
|
|
CONFIG_REGMAP_SPI=y
|
|
|
|
|
CONFIG_REGULATOR=y
|
|
|
|
|
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
|
|
|
|
# CONFIG_REGULATOR_QCOM_SPMI is not set
|
|
|
|
|
CONFIG_REGULATOR_VCTRL=y
|
2020-03-08 16:21:44 +00:00
|
|
|
CONFIG_REGULATOR_VQMMC_IPQ4019=y
|
2018-12-16 22:04:50 +00:00
|
|
|
CONFIG_RESET_CONTROLLER=y
|
|
|
|
|
# CONFIG_RESET_QCOM_AOSS is not set
|
|
|
|
|
CONFIG_RFS_ACCEL=y
|
|
|
|
|
CONFIG_RPS=y
|
|
|
|
|
CONFIG_RTC_CLASS=y
|
|
|
|
|
# CONFIG_RTC_DRV_CMOS is not set
|
|
|
|
|
CONFIG_RTC_I2C_AND_SPI=y
|
|
|
|
|
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
|
|
|
|
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
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# CONFIG_SDM_DISPCC_845 is not set
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# CONFIG_SDM_GCC_845 is not set
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# CONFIG_SDM_VIDEOCC_845 is not set
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CONFIG_SERIAL_8250_FSL=y
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# CONFIG_SERIAL_AMBA_PL011 is not set
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CONFIG_SERIAL_MSM=y
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CONFIG_SERIAL_MSM_CONSOLE=y
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CONFIG_SGL_ALLOC=y
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CONFIG_SMP=y
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CONFIG_SMP_ON_UP=y
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CONFIG_SPARSE_IRQ=y
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CONFIG_SPI=y
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CONFIG_SPI_BITBANG=y
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CONFIG_SPI_GPIO=y
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CONFIG_SPI_MASTER=y
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CONFIG_SPI_MEM=y
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CONFIG_SPI_QUP=y
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CONFIG_SPMI=y
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CONFIG_SPMI_MSM_PMIC_ARB=y
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# CONFIG_SPMI_PMIC_CLKDIV is not set
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CONFIG_SRCU=y
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CONFIG_SWCONFIG=y
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CONFIG_SWCONFIG_LEDS=y
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CONFIG_SWPHY=y
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CONFIG_SWP_EMULATE=y
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CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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CONFIG_TEE=y
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CONFIG_THERMAL=y
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CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
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CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
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|
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CONFIG_THERMAL_GOV_STEP_WISE=y
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CONFIG_THERMAL_OF=y
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|
|
# CONFIG_THUMB2_KERNEL is not set
|
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|
|
CONFIG_TICK_CPU_ACCOUNTING=y
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|
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|
CONFIG_TIMER_OF=y
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|
CONFIG_TIMER_PROBE=y
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|
CONFIG_TREE_RCU=y
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|
|
CONFIG_TREE_SRCU=y
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|
|
CONFIG_UBIFS_FS=y
|
|
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|
|
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
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|
|
|
CONFIG_UBIFS_FS_LZO=y
|
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|
|
|
CONFIG_UBIFS_FS_ZLIB=y
|
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|
|
|
CONFIG_UEVENT_HELPER_PATH=""
|
|
|
|
|
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
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|
|
|
CONFIG_USB=y
|
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|
|
|
CONFIG_USB_COMMON=y
|
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|
|
|
# CONFIG_USB_EHCI_HCD is not set
|
|
|
|
|
CONFIG_USB_SUPPORT=y
|
|
|
|
|
CONFIG_USE_OF=y
|
|
|
|
|
CONFIG_VDSO=y
|
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|
|
|
CONFIG_VFP=y
|
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|
|
|
CONFIG_VFPv3=y
|
|
|
|
|
CONFIG_WATCHDOG_CORE=y
|
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|
|
|
CONFIG_XPS=y
|
|
|
|
|
CONFIG_XZ_DEC_ARM=y
|
|
|
|
|
CONFIG_XZ_DEC_BCJ=y
|
|
|
|
|
CONFIG_ZBOOT_ROM_BSS=0
|
|
|
|
|
CONFIG_ZBOOT_ROM_TEXT=0
|
|
|
|
|
CONFIG_ZLIB_DEFLATE=y
|
|
|
|
|
CONFIG_ZLIB_INFLATE=y
|
