2023-08-26 01:19:18 +00:00
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From 1e25ca1147579bda8b941be1b9851f5911d44eb0 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 22 Aug 2023 19:04:42 +0100
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Subject: [PATCH 098/125] net: ethernet: mtk_eth_soc: add paths and SerDes
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modes for MT7988
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MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
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connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
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2500Base-X, 1000Base-X and Cisco SGMII interface modes.
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Implement support for configuring for the new paths to SerDes interfaces
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and the internal 2.5G PHY.
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Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and
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setup the new PHYA on MT7988 to access the also still existing old
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LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface
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modes.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/ethernet/mediatek/Kconfig | 16 +
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drivers/net/ethernet/mediatek/Makefile | 1 +
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drivers/net/ethernet/mediatek/mtk_eth_path.c | 123 +++-
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 182 ++++-
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 232 ++++++-
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drivers/net/ethernet/mediatek/mtk_usxgmii.c | 692 +++++++++++++++++++
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6 files changed, 1215 insertions(+), 31 deletions(-)
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create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c
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--- a/drivers/net/ethernet/mediatek/Kconfig
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+++ b/drivers/net/ethernet/mediatek/Kconfig
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@@ -25,6 +25,22 @@ config NET_MEDIATEK_SOC
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This driver supports the gigabit ethernet MACs in the
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MediaTek SoC family.
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+config NET_MEDIATEK_SOC_USXGMII
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+ bool "Support USXGMII SerDes on MT7988"
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+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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+ def_bool NET_MEDIATEK_SOC != n
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+ help
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+ Include support for 10GE SerDes which can be found on MT7988.
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+ If this kernel should run on SoCs with 10 GBit/s Ethernet you
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+ will need to select this option to use GMAC2 and GMAC3 with
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+ external PHYs, SFP(+) cages in 10GBase-R, 5GBase-R or USXGMII
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+ interface modes.
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+
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+ Note that as the 2500Base-X/1000Base-X/Cisco SGMII SerDes PCS
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+ unit (MediaTek LynxI) in MT7988 is connected via the new 10GE
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+ SerDes, you will also need to select this option in case you
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+ want to use any of those SerDes modes.
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+
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config NET_MEDIATEK_STAR_EMAC
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tristate "MediaTek STAR Ethernet MAC support"
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select PHYLIB
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--- a/drivers/net/ethernet/mediatek/Makefile
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+++ b/drivers/net/ethernet/mediatek/Makefile
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@@ -5,6 +5,7 @@
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obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
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mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
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+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o
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mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
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ifdef CONFIG_DEBUG_FS
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mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
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--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
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@@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
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return "gmac2_rgmii";
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case MTK_ETH_PATH_GMAC2_SGMII:
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return "gmac2_sgmii";
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+ case MTK_ETH_PATH_GMAC2_2P5GPHY:
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+ return "gmac2_2p5gphy";
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case MTK_ETH_PATH_GMAC2_GEPHY:
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return "gmac2_gephy";
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+ case MTK_ETH_PATH_GMAC3_SGMII:
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+ return "gmac3_sgmii";
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case MTK_ETH_PATH_GDM1_ESW:
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return "gdm1_esw";
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+ case MTK_ETH_PATH_GMAC1_USXGMII:
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+ return "gmac1_usxgmii";
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+ case MTK_ETH_PATH_GMAC2_USXGMII:
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+ return "gmac2_usxgmii";
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+ case MTK_ETH_PATH_GMAC3_USXGMII:
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+ return "gmac3_usxgmii";
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default:
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return "unknown path";
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}
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@@ -127,6 +137,27 @@ static int set_mux_u3_gmac2_to_qphy(stru
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return 0;
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}
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+static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path)
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+{
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+ int ret;
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+
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+ if (path == MTK_ETH_PATH_GMAC2_2P5GPHY) {
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+ ret = regmap_clear_bits(eth->ethsys, ETHSYS_SYSCFG0, SYSCFG0_SGMII_GMAC2_V2);
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+ if (ret)
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+ return ret;
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+
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+ /* Setup mux to 2p5g PHY */
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+ ret = regmap_clear_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX, MUX_G2_USXGMII_SEL);
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+ if (ret)
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+ return ret;
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+
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+ dev_dbg(eth->dev, "path %s in %s updated\n",
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+ mtk_eth_path_name(path), __func__);
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+ }
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+
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+ return 0;
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+}
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+
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static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
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{
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unsigned int val = 0;
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@@ -165,7 +196,48 @@ static int set_mux_gmac1_gmac2_to_sgmii_
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return 0;
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}
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-static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
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+static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path)
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+{
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+ unsigned int val = 0;
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+ bool updated = true;
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+ int mac_id = 0;
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+
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+ /* Disable SYSCFG1 SGMII */
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+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
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+
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+ switch (path) {
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+ case MTK_ETH_PATH_GMAC1_USXGMII:
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+ val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2;
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+ mac_id = MTK_GMAC1_ID;
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+ break;
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+ case MTK_ETH_PATH_GMAC2_USXGMII:
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+ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
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+ mac_id = MTK_GMAC2_ID;
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+ break;
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+ case MTK_ETH_PATH_GMAC3_USXGMII:
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+ val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2;
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+ mac_id = MTK_GMAC3_ID;
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+ break;
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+ default:
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+ updated = false;
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+ };
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+
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+ if (updated) {
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+ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
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+ SYSCFG0_SGMII_MASK, val);
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+
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+ if (mac_id == MTK_GMAC2_ID)
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+ regmap_set_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX,
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+ MUX_G2_USXGMII_SEL);
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+ }
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+
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+ dev_dbg(eth->dev, "path %s in %s updated = %d\n",
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+ mtk_eth_path_name(path), __func__, updated);
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+
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+ return 0;
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+}
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+
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+static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
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{
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unsigned int val = 0;
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bool updated = true;
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@@ -182,6 +254,9 @@ static int set_mux_gmac12_to_gephy_sgmii
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case MTK_ETH_PATH_GMAC2_SGMII:
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val |= SYSCFG0_SGMII_GMAC2_V2;
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break;
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+ case MTK_ETH_PATH_GMAC3_SGMII:
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+ val |= SYSCFG0_SGMII_GMAC3_V2;
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+ break;
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default:
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updated = false;
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}
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@@ -210,13 +285,25 @@ static const struct mtk_eth_muxc mtk_eth
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.cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
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.set_path = set_mux_u3_gmac2_to_qphy,
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}, {
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+ .name = "mux_gmac2_to_2p5gphy",
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+ .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
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+ .set_path = set_mux_gmac2_to_2p5gphy,
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+ }, {
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.name = "mux_gmac1_gmac2_to_sgmii_rgmii",
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.cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
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.set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii,
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}, {
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.name = "mux_gmac12_to_gephy_sgmii",
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.cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
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- .set_path = set_mux_gmac12_to_gephy_sgmii,
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+ .set_path = set_mux_gmac123_to_gephy_sgmii,
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+ }, {
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+ .name = "mux_gmac123_to_gephy_sgmii",
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+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII,
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+ .set_path = set_mux_gmac123_to_gephy_sgmii,
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+ }, {
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+ .name = "mux_gmac123_to_usxgmii",
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+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII,
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+ .set_path = set_mux_gmac123_to_usxgmii,
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},
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};
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@@ -249,12 +336,39 @@ out:
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return err;
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}
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+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id)
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+{
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+ u64 path;
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+
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+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII :
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+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII :
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+ MTK_ETH_PATH_GMAC3_USXGMII;
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+
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+ /* Setup proper MUXes along the path */
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+ return mtk_eth_mux_setup(eth, path);
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+}
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+
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int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
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{
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u64 path;
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- path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
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- MTK_ETH_PATH_GMAC2_SGMII;
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+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII :
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+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII :
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+ MTK_ETH_PATH_GMAC3_SGMII;
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+
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+ /* Setup proper MUXes along the path */
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+ return mtk_eth_mux_setup(eth, path);
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+}
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+
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+int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id)
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+{
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+ u64 path = 0;
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+
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+ if (mac_id == MTK_GMAC2_ID)
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+ path = MTK_ETH_PATH_GMAC2_2P5GPHY;
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+
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+ if (!path)
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+ return -EINVAL;
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/* Setup proper MUXes along the path */
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return mtk_eth_mux_setup(eth, path);
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@@ -284,4 +398,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk
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/* Setup proper MUXes along the path */
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return mtk_eth_mux_setup(eth, path);
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}
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-
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -474,6 +474,30 @@ static void mtk_setup_bridge_switch(stru
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MTK_GSW_CFG);
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}
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+static bool mtk_check_gmac23_idle(struct mtk_mac *mac)
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+{
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+ u32 mac_fsm, gdm_fsm;
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+
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+ mac_fsm = mtk_r32(mac->hw, MTK_MAC_FSM(mac->id));
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+
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+ switch (mac->id) {
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+ case MTK_GMAC2_ID:
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+ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM2_FSM);
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+ break;
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+ case MTK_GMAC3_ID:
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+ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM3_FSM);
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+ break;
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+ default:
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+ return true;
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+ };
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+
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+ if ((mac_fsm & 0xFFFF0000) == 0x01010000 &&
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+ (gdm_fsm & 0xFFFF0000) == 0x00000000)
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+ return true;
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+
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+ return false;
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+}
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+
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static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
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phy_interface_t interface)
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{
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@@ -482,12 +506,20 @@ static struct phylink_pcs *mtk_mac_selec
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struct mtk_eth *eth = mac->hw;
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unsigned int sid;
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- if (interface == PHY_INTERFACE_MODE_SGMII ||
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- phy_interface_mode_is_8023z(interface)) {
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- sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
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- 0 : mac->id;
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-
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- return eth->sgmii_pcs[sid];
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+ if ((interface == PHY_INTERFACE_MODE_SGMII ||
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+ phy_interface_mode_is_8023z(interface)) &&
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+ MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
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+ sid = mtk_mac2xgmii_id(eth, mac->id);
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII))
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+ return mtk_sgmii_wrapper_select_pcs(eth, mac->id);
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+ else
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+ return eth->sgmii_pcs[sid];
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+ } else if ((interface == PHY_INTERFACE_MODE_USXGMII ||
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+ interface == PHY_INTERFACE_MODE_10GBASER ||
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+ interface == PHY_INTERFACE_MODE_5GBASER) &&
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+ MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII) &&
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+ mac->id != MTK_GMAC1_ID) {
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+ return mtk_usxgmii_select_pcs(eth, mac->id);
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
@@ -543,7 +575,22 @@ static void mtk_mac_config(struct phylin
|
|
|
|
goto init_err;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
+ case PHY_INTERFACE_MODE_USXGMII:
|
|
|
|
+ case PHY_INTERFACE_MODE_10GBASER:
|
|
|
|
+ case PHY_INTERFACE_MODE_5GBASER:
|
|
|
|
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
|
|
|
|
+ err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
|
|
|
|
+ if (err)
|
|
|
|
+ goto init_err;
|
|
|
|
+ }
|
|
|
|
+ break;
|
|
|
|
case PHY_INTERFACE_MODE_INTERNAL:
|
|
|
|
+ if (mac->id == MTK_GMAC2_ID &&
|
|
|
|
+ MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
|
|
|
|
+ err = mtk_gmac_2p5gphy_path_setup(eth, mac->id);
|
|
|
|
+ if (err)
|
|
|
|
+ goto init_err;
|
|
|
|
+ }
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
goto err_phy;
|
|
|
|
@@ -598,8 +645,6 @@ static void mtk_mac_config(struct phylin
|
|
|
|
val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
|
|
|
|
val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
|
|
|
|
regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
|
|
|
|
-
|
|
|
|
- mac->interface = state->interface;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* SGMII */
|
|
|
|
@@ -616,21 +661,40 @@ static void mtk_mac_config(struct phylin
|
|
|
|
|
|
|
|
/* Save the syscfg0 value for mac_finish */
|
|
|
|
mac->syscfg0 = val;
|
|
|
|
- } else if (phylink_autoneg_inband(mode)) {
|
|
|
|
+ } else if (state->interface != PHY_INTERFACE_MODE_USXGMII &&
|
|
|
|
+ state->interface != PHY_INTERFACE_MODE_10GBASER &&
|
|
|
|
+ state->interface != PHY_INTERFACE_MODE_5GBASER &&
|
|
|
|
+ phylink_autoneg_inband(mode)) {
|
|
|
|
dev_err(eth->dev,
|
|
|
|
- "In-band mode not supported in non SGMII mode!\n");
|
|
|
|
+ "In-band mode not supported in non-SerDes modes!\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup gmac */
|
|
|
|
- if (mtk_is_netsys_v3_or_greater(eth) &&
|
|
|
|
- mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
|
|
|
|
- mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
|
|
|
|
- mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
|
|
|
|
+ if (mtk_is_netsys_v3_or_greater(eth)) {
|
|
|
|
+ if (mtk_interface_mode_is_xgmii(state->interface)) {
|
|
|
|
+ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
|
|
|
|
+ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
|
|
|
|
+
|
|
|
|
+ if (mac->id == MTK_GMAC1_ID)
|
|
|
|
+ mtk_setup_bridge_switch(eth);
|
|
|
|
+ } else {
|
|
|
|
+ mtk_w32(eth, 0, MTK_GDMA_EG_CTRL(mac->id));
|
|
|
|
|
|
|
|
- mtk_setup_bridge_switch(eth);
|
|
|
|
+ /* FIXME: In current hardware design, we have to reset FE
|
|
|
|
+ * when swtiching XGDM to GDM. Therefore, here trigger an SER
|
|
|
|
+ * to let GDM go back to the initial state.
|
|
|
|
+ */
|
|
|
|
+ if ((mtk_interface_mode_is_xgmii(mac->interface) ||
|
|
|
|
+ mac->interface == PHY_INTERFACE_MODE_NA) &&
|
|
|
|
+ !mtk_check_gmac23_idle(mac) &&
|
|
|
|
+ !test_bit(MTK_RESETTING, ð->state))
|
|
|
|
+ schedule_work(ð->pending_work);
|
|
|
|
+ }
|
|
|
|
}
|
|
|
|
|
|
|
|
+ mac->interface = state->interface;
|
|
|
|
+
|
|
|
|
return;
|
|
|
|
|
|
|
|
err_phy:
|
|
|
|
@@ -676,10 +740,13 @@ static void mtk_mac_link_down(struct phy
|
|
|
|
{
|
|
|
|
struct mtk_mac *mac = container_of(config, struct mtk_mac,
|
|
|
|
phylink_config);
|
|
|
|
- u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
|
|
|
|
|
|
|
|
- mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
|
|
|
|
- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
|
|
|
|
+ if (!mtk_interface_mode_is_xgmii(interface)) {
|
|
|
|
+ mtk_m32(mac->hw, MAC_MCR_TX_EN | MAC_MCR_RX_EN, 0, MTK_MAC_MCR(mac->id));
|
|
|
|
+ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, MTK_XGMAC_STS(mac->id));
|
|
|
|
+ } else if (mac->id != MTK_GMAC1_ID) {
|
|
|
|
+ mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id));
|
|
|
|
+ }
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
|
|
|
|
@@ -751,13 +818,11 @@ static void mtk_set_queue_speed(struct m
|
|
|
|
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
|
|
|
|
}
|
|
|
|
|
|
|
|
-static void mtk_mac_link_up(struct phylink_config *config,
|
|
|
|
- struct phy_device *phy,
|
|
|
|
- unsigned int mode, phy_interface_t interface,
|
|
|
|
- int speed, int duplex, bool tx_pause, bool rx_pause)
|
|
|
|
+static void mtk_gdm_mac_link_up(struct mtk_mac *mac,
|
|
|
|
+ struct phy_device *phy,
|
|
|
|
+ unsigned int mode, phy_interface_t interface,
|
|
|
|
+ int speed, int duplex, bool tx_pause, bool rx_pause)
|
|
|
|
{
|
|
|
|
- struct mtk_mac *mac = container_of(config, struct mtk_mac,
|
|
|
|
- phylink_config);
|
|
|
|
u32 mcr;
|
|
|
|
|
|
|
|
mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
|
|
|
|
@@ -791,6 +856,55 @@ static void mtk_mac_link_up(struct phyli
|
|
|
|
mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
|
|
|
|
}
|
|
|
|
|
|
|
|
+static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
|
|
|
|
+ struct phy_device *phy,
|
|
|
|
+ unsigned int mode, phy_interface_t interface,
|
|
|
|
+ int speed, int duplex, bool tx_pause, bool rx_pause)
|
|
|
|
+{
|
|
|
|
+ u32 mcr, force_link = 0;
|
|
|
|
+
|
|
|
|
+ if (mac->id == MTK_GMAC1_ID)
|
|
|
|
+ return;
|
|
|
|
+
|
|
|
|
+ /* Eliminate the interference(before link-up) caused by PHY noise */
|
|
|
|
+ mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id));
|
|
|
|
+ mdelay(20);
|
|
|
|
+ mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id));
|
|
|
|
+
|
|
|
|
+ if (mac->interface == PHY_INTERFACE_MODE_INTERNAL || mac->id == MTK_GMAC3_ID)
|
|
|
|
+ force_link = MTK_XGMAC_FORCE_LINK(mac->id);
|
|
|
|
+
|
|
|
|
+ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), force_link, MTK_XGMAC_STS(mac->id));
|
|
|
|
+
|
|
|
|
+ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
|
|
|
|
+ mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | XMAC_MCR_TRX_DISABLE);
|
|
|
|
+ /* Configure pause modes -
|
|
|
|
+ * phylink will avoid these for half duplex
|
|
|
|
+ */
|
|
|
|
+ if (tx_pause)
|
|
|
|
+ mcr |= XMAC_MCR_FORCE_TX_FC;
|
|
|
|
+ if (rx_pause)
|
|
|
|
+ mcr |= XMAC_MCR_FORCE_RX_FC;
|
|
|
|
+
|
|
|
|
+ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void mtk_mac_link_up(struct phylink_config *config,
|
|
|
|
+ struct phy_device *phy,
|
|
|
|
+ unsigned int mode, phy_interface_t interface,
|
|
|
|
+ int speed, int duplex, bool tx_pause, bool rx_pause)
|
|
|
|
+{
|
|
|
|
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
|
|
|
|
+ phylink_config);
|
|
|
|
+
|
|
|
|
+ if (mtk_interface_mode_is_xgmii(interface))
|
|
|
|
+ mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
|
|
|
|
+ tx_pause, rx_pause);
|
|
|
|
+ else
|
|
|
|
+ mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
|
|
|
|
+ tx_pause, rx_pause);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
static const struct phylink_mac_ops mtk_phylink_ops = {
|
|
|
|
.validate = phylink_generic_validate,
|
|
|
|
.mac_select_pcs = mtk_mac_select_pcs,
|
2023-09-19 18:00:07 +00:00
|
|
|
@@ -4616,8 +4730,21 @@ static int mtk_add_mac(struct mtk_eth *e
|
2023-08-26 01:19:18 +00:00
|
|
|
phy_interface_zero(mac->phylink_config.supported_interfaces);
|
|
|
|
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
|
|
|
|
mac->phylink_config.supported_interfaces);
|
|
|
|
+ } else if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) {
|
|
|
|
+ mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD;
|
|
|
|
+ __set_bit(PHY_INTERFACE_MODE_5GBASER,
|
|
|
|
+ mac->phylink_config.supported_interfaces);
|
|
|
|
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
|
|
|
|
+ mac->phylink_config.supported_interfaces);
|
|
|
|
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
|
|
|
|
+ mac->phylink_config.supported_interfaces);
|
|
|
|
}
|
|
|
|
|
|
|
|
+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) &&
|
|
|
|
+ id == MTK_GMAC2_ID)
|
|
|
|
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
|
|
|
|
+ mac->phylink_config.supported_interfaces);
|
|
|
|
+
|
|
|
|
phylink = phylink_create(&mac->phylink_config,
|
|
|
|
of_fwnode_handle(mac->of_node),
|
|
|
|
phy_mode, &mtk_phylink_ops);
|
2023-09-19 18:00:07 +00:00
|
|
|
@@ -4810,6 +4937,13 @@ static int mtk_probe(struct platform_dev
|
2023-08-26 01:19:18 +00:00
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
|
|
|
|
+ err = mtk_usxgmii_init(eth);
|
|
|
|
+
|
|
|
|
+ if (err)
|
|
|
|
+ return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (eth->soc->required_pctl) {
|
|
|
|
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
|
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
|
|
|
@@ -502,6 +502,21 @@
|
|
|
|
#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
|
|
|
|
#define INTF_MODE_RGMII_10_100 0
|
|
|
|
|
|
|
|
+/* XFI Mac control registers */
|
|
|
|
+#define MTK_XMAC_BASE(x) (0x12000 + (((x) - 1) * 0x1000))
|
|
|
|
+#define MTK_XMAC_MCR(x) (MTK_XMAC_BASE(x))
|
|
|
|
+#define XMAC_MCR_TRX_DISABLE 0xf
|
|
|
|
+#define XMAC_MCR_FORCE_TX_FC BIT(5)
|
|
|
|
+#define XMAC_MCR_FORCE_RX_FC BIT(4)
|
|
|
|
+
|
|
|
|
+/* XFI Mac logic reset registers */
|
|
|
|
+#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10)
|
|
|
|
+#define XMAC_LOGIC_RST BIT(0)
|
|
|
|
+
|
|
|
|
+/* XFI Mac count global control */
|
|
|
|
+#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100)
|
|
|
|
+#define XMAC_GLB_CNTCLR BIT(0)
|
|
|
|
+
|
|
|
|
/* GPIO port control registers for GMAC 2*/
|
|
|
|
#define GPIO_OD33_CTRL8 0x4c0
|
|
|
|
#define GPIO_BIAS_CTRL 0xed0
|
|
|
|
@@ -527,6 +542,7 @@
|
|
|
|
#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
|
|
|
|
#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
|
|
|
|
#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
|
|
|
|
+#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)
|
|
|
|
|
|
|
|
|
|
|
|
/* ethernet subsystem clock register */
|
|
|
|
@@ -559,12 +575,74 @@
|
|
|
|
#define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
|
|
|
|
#define ETHSYS_DMA_AG_MAP_PPE BIT(2)
|
|
|
|
|
|
|
|
+/* USXGMII subsystem config registers */
|
|
|
|
+/* Register to control speed */
|
|
|
|
+#define RG_PHY_TOP_SPEED_CTRL1 0x80C
|
|
|
|
+#define USXGMII_RATE_UPDATE_MODE BIT(31)
|
|
|
|
+#define USXGMII_MAC_CK_GATED BIT(29)
|
|
|
|
+#define USXGMII_IF_FORCE_EN BIT(28)
|
|
|
|
+#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8)
|
|
|
|
+#define USXGMII_RATE_ADAPT_MODE_X1 0
|
|
|
|
+#define USXGMII_RATE_ADAPT_MODE_X2 1
|
|
|
|
+#define USXGMII_RATE_ADAPT_MODE_X4 2
|
|
|
|
+#define USXGMII_RATE_ADAPT_MODE_X10 3
|
|
|
|
+#define USXGMII_RATE_ADAPT_MODE_X100 4
|
|
|
|
+#define USXGMII_RATE_ADAPT_MODE_X5 5
|
|
|
|
+#define USXGMII_RATE_ADAPT_MODE_X50 6
|
|
|
|
+#define USXGMII_XFI_RX_MODE GENMASK(6, 4)
|
|
|
|
+#define USXGMII_XFI_RX_MODE_10G 0
|
|
|
|
+#define USXGMII_XFI_RX_MODE_5G 1
|
|
|
|
+#define USXGMII_XFI_TX_MODE GENMASK(2, 0)
|
|
|
|
+#define USXGMII_XFI_TX_MODE_10G 0
|
|
|
|
+#define USXGMII_XFI_TX_MODE_5G 1
|
|
|
|
+
|
|
|
|
+/* Register to control PCS AN */
|
|
|
|
+#define RG_PCS_AN_CTRL0 0x810
|
|
|
|
+#define USXGMII_AN_RESTART BIT(31)
|
|
|
|
+#define USXGMII_AN_SYNC_CNT GENMASK(30, 11)
|
|
|
|
+#define USXGMII_AN_ENABLE BIT(0)
|
|
|
|
+
|
|
|
|
+#define RG_PCS_AN_CTRL2 0x818
|
|
|
|
+#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20)
|
|
|
|
+#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10)
|
|
|
|
+#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0)
|
|
|
|
+
|
|
|
|
+/* Register to read PCS AN status */
|
|
|
|
+#define RG_PCS_AN_STS0 0x81c
|
|
|
|
+#define USXGMII_PCS_AN_WORD GENMASK(15, 0)
|
|
|
|
+#define USXGMII_LPA_LATCH BIT(31)
|
|
|
|
+
|
|
|
|
+/* Register to control USXGMII XFI PLL digital */
|
|
|
|
+#define XFI_PLL_DIG_GLB8 0x08
|
|
|
|
+#define RG_XFI_PLL_EN BIT(31)
|
|
|
|
+
|
|
|
|
+/* Register to control USXGMII XFI PLL analog */
|
|
|
|
+#define XFI_PLL_ANA_GLB8 0x108
|
|
|
|
+#define RG_XFI_PLL_ANA_SWWA 0x02283248
|
|
|
|
+
|
|
|
|
/* Infrasys subsystem config registers */
|
|
|
|
#define INFRA_MISC2 0x70c
|
|
|
|
#define CO_QPHY_SEL BIT(0)
|
|
|
|
#define GEPHY_MAC_SEL BIT(1)
|
|
|
|
|
|
|
|
+/* Toprgu subsystem config registers */
|
|
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|
+#define TOPRGU_SWSYSRST 0x18
|
|
|
|
+#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24)
|
|
|
|
+#define SWSYSRST_XFI_PLL_GRST BIT(16)
|
|
|
|
+#define SWSYSRST_XFI_PEXPT1_GRST BIT(15)
|
|
|
|
+#define SWSYSRST_XFI_PEXPT0_GRST BIT(14)
|
|
|
|
+#define SWSYSRST_XFI1_GRST BIT(13)
|
|
|
|
+#define SWSYSRST_XFI0_GRST BIT(12)
|
|
|
|
+#define SWSYSRST_SGMII1_GRST BIT(2)
|
|
|
|
+#define SWSYSRST_SGMII0_GRST BIT(1)
|
|
|
|
+#define TOPRGU_SWSYSRST_EN 0xFC
|
|
|
|
+
|
|
|
|
/* Top misc registers */
|
|
|
|
+#define TOP_MISC_NETSYS_PCS_MUX 0x84
|
|
|
|
+#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
|
|
|
|
+#define MUX_G2_USXGMII_SEL BIT(1)
|
|
|
|
+#define MUX_HSGMII1_G1_SEL BIT(0)
|
|
|
|
+
|
|
|
|
#define USB_PHY_SWITCH_REG 0x218
|
|
|
|
#define QPHY_SEL_MASK GENMASK(1, 0)
|
|
|
|
#define SGMII_QPHY_SEL 0x2
|
|
|
|
@@ -589,6 +667,8 @@
|
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|
|
#define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
|
|
|
|
#define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
|
|
|
|
|
|
|
|
+/* Debug Purpose Register */
|
|
|
|
+#define MTK_PSE_FQFC_CFG 0x100
|
|
|
|
#define MTK_FE_CDM1_FSM 0x220
|
|
|
|
#define MTK_FE_CDM2_FSM 0x224
|
|
|
|
#define MTK_FE_CDM3_FSM 0x238
|
|
|
|
@@ -597,6 +677,11 @@
|
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|
|
#define MTK_FE_CDM6_FSM 0x328
|
|
|
|
#define MTK_FE_GDM1_FSM 0x228
|
|
|
|
#define MTK_FE_GDM2_FSM 0x22C
|
|
|
|
+#define MTK_FE_GDM3_FSM 0x23C
|
|
|
|
+#define MTK_FE_PSE_FREE 0x240
|
|
|
|
+#define MTK_FE_DROP_FQ 0x244
|
|
|
|
+#define MTK_FE_DROP_FC 0x248
|
|
|
|
+#define MTK_FE_DROP_PPE 0x24C
|
|
|
|
|
|
|
|
#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
|
|
|
|
|
|
|
|
@@ -943,6 +1028,8 @@ enum mkt_eth_capabilities {
|
|
|
|
MTK_RGMII_BIT = 0,
|
|
|
|
MTK_TRGMII_BIT,
|
|
|
|
MTK_SGMII_BIT,
|
|
|
|
+ MTK_USXGMII_BIT,
|
|
|
|
+ MTK_2P5GPHY_BIT,
|
|
|
|
MTK_ESW_BIT,
|
|
|
|
MTK_GEPHY_BIT,
|
|
|
|
MTK_MUX_BIT,
|
|
|
|
@@ -963,8 +1050,11 @@ enum mkt_eth_capabilities {
|
|
|
|
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
|
|
|
|
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
|
|
|
|
MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
|
|
|
|
+ MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
|
|
|
|
MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
|
|
|
|
MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
|
|
|
|
+ MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
|
|
|
|
+ MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT,
|
|
|
|
|
|
|
|
/* PATH BITS */
|
|
|
|
MTK_ETH_PATH_GMAC1_RGMII_BIT,
|
|
|
|
@@ -972,14 +1062,21 @@ enum mkt_eth_capabilities {
|
|
|
|
MTK_ETH_PATH_GMAC1_SGMII_BIT,
|
|
|
|
MTK_ETH_PATH_GMAC2_RGMII_BIT,
|
|
|
|
MTK_ETH_PATH_GMAC2_SGMII_BIT,
|
|
|
|
+ MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
|
|
|
|
MTK_ETH_PATH_GMAC2_GEPHY_BIT,
|
|
|
|
+ MTK_ETH_PATH_GMAC3_SGMII_BIT,
|
|
|
|
MTK_ETH_PATH_GDM1_ESW_BIT,
|
|
|
|
+ MTK_ETH_PATH_GMAC1_USXGMII_BIT,
|
|
|
|
+ MTK_ETH_PATH_GMAC2_USXGMII_BIT,
|
|
|
|
+ MTK_ETH_PATH_GMAC3_USXGMII_BIT,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Supported hardware group on SoCs */
|
|
|
|
#define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
|
|
|
|
#define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
|
|
|
|
#define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
|
|
|
|
+#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT)
|
|
|
|
+#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
|
|
|
|
#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
|
|
|
|
#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
|
|
|
|
#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
|
|
|
|
@@ -1002,10 +1099,16 @@ enum mkt_eth_capabilities {
|
|
|
|
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
|
|
|
|
#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
|
|
|
|
BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
|
|
|
|
+#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
|
|
|
|
+ BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
|
|
|
|
#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
|
|
|
|
BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
|
|
|
|
#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
|
|
|
|
BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
|
|
|
|
+#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \
|
|
|
|
+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT)
|
|
|
|
+#define MTK_ETH_MUX_GMAC123_TO_USXGMII \
|
|
|
|
+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT)
|
|
|
|
|
|
|
|
/* Supported path present on SoCs */
|
|
|
|
#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
|
|
|
|
@@ -1013,8 +1116,13 @@ enum mkt_eth_capabilities {
|
|
|
|
#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
|
|
|
|
#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
|
|
|
|
#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
|
|
|
|
+#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
|
|
|
|
#define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
|
|
|
|
+#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
|
|
|
|
#define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
|
|
|
|
+#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT)
|
|
|
|
+#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT)
|
|
|
|
+#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT)
|
|
|
|
|
|
|
|
#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
|
|
|
|
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
|
|
|
|
@@ -1022,7 +1130,12 @@ enum mkt_eth_capabilities {
|
|
|
|
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
|
|
|
|
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
|
|
|
|
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
|
|
|
|
+#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
|
|
|
|
+#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
|
|
|
|
#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
|
|
|
|
+#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
|
|
|
|
+#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
|
|
|
|
+#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
|
|
|
|
|
|
|
|
/* MUXes present on SoCs */
|
|
|
|
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
|
|
|
|
@@ -1041,10 +1154,20 @@ enum mkt_eth_capabilities {
|
|
|
|
(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
|
|
|
|
MTK_SHARED_SGMII)
|
|
|
|
|
|
|
|
+/* 2: GMAC2 -> XGMII */
|
|
|
|
+#define MTK_MUX_GMAC2_TO_2P5GPHY \
|
|
|
|
+ (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA)
|
|
|
|
+
|
|
|
|
/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
|
|
|
|
#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
|
|
|
|
(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
|
|
|
|
|
|
|
|
+#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \
|
|
|
|
+ (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX)
|
|
|
|
+
|
|
|
|
+#define MTK_MUX_GMAC123_TO_USXGMII \
|
|
|
|
+ (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA)
|
|
|
|
+
|
|
|
|
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
|
|
|
|
|
|
|
|
#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
|
|
|
|
@@ -1076,8 +1199,12 @@ enum mkt_eth_capabilities {
|
|
|
|
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
|
|
|
|
MTK_RSTCTRL_PPE1 | MTK_SRAM)
|
|
|
|
|
|
|
|
-#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
|
|
|
|
- MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
|
|
|
|
+#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
|
|
|
|
+ MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
|
|
|
|
+ MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \
|
|
|
|
+ MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
|
|
|
|
+ MTK_MUX_GMAC123_TO_USXGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
|
|
|
|
+ MTK_QDMA | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
|
|
|
|
|
|
|
|
struct mtk_tx_dma_desc_info {
|
|
|
|
dma_addr_t addr;
|
|
|
|
@@ -1187,6 +1314,24 @@ struct mtk_soc_data {
|
|
|
|
/* currently no SoC has more than 3 macs */
|
|
|
|
#define MTK_MAX_DEVS 3
|
|
|
|
|
|
|
|
+/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and
|
|
|
|
+ * associated data
|
|
|
|
+ * @regmap: The register map pointing at the range used to setup
|
|
|
|
+ * USXGMII modes
|
|
|
|
+ * @interface: Currently selected interface mode
|
|
|
|
+ * @id: The element is used to record the index of PCS
|
|
|
|
+ * @pcs: Phylink PCS structure
|
|
|
|
+ */
|
|
|
|
+struct mtk_usxgmii_pcs {
|
|
|
|
+ struct mtk_eth *eth;
|
|
|
|
+ struct regmap *regmap;
|
|
|
|
+ struct phylink_pcs *wrapped_sgmii_pcs;
|
|
|
|
+ phy_interface_t interface;
|
|
|
|
+ u8 id;
|
|
|
|
+ unsigned int mode;
|
|
|
|
+ struct phylink_pcs pcs;
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
/* struct mtk_eth - This is the main datasructure for holding the state
|
|
|
|
* of the driver
|
|
|
|
* @dev: The device pointer
|
|
|
|
@@ -1207,6 +1352,12 @@ struct mtk_soc_data {
|
|
|
|
* @infra: The register map pointing at the range used to setup
|
|
|
|
* SGMII and GePHY path
|
|
|
|
* @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances
|
|
|
|
+ * @sgmii_wrapped_pcs: Pointers to NETSYSv3 wrapper PCS instances
|
|
|
|
+ * @usxgmii_pll: The register map pointing at the range used to control
|
|
|
|
+ * the USXGMII SerDes PLL
|
|
|
|
+ * @regmap_pextp: The register map pointing at the range used to setup
|
|
|
|
+ * PHYA
|
|
|
|
+ * @usxgmii_pcs: Pointer to array of pointers to struct for USXGMII PCS
|
|
|
|
* @pctl: The register map pointing at the range used to setup
|
|
|
|
* GMAC port drive/slew values
|
|
|
|
* @dma_refcnt: track how many netdevs are using the DMA engine
|
|
|
|
@@ -1250,6 +1401,10 @@ struct mtk_eth {
|
|
|
|
struct regmap *ethsys;
|
|
|
|
struct regmap *infra;
|
|
|
|
struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS];
|
|
|
|
+ struct regmap *toprgu;
|
|
|
|
+ struct regmap *usxgmii_pll;
|
|
|
|
+ struct regmap *regmap_pextp[MTK_MAX_DEVS];
|
|
|
|
+ struct mtk_usxgmii_pcs *usxgmii_pcs[MTK_MAX_DEVS];
|
|
|
|
struct regmap *pctl;
|
|
|
|
bool hwlro;
|
|
|
|
refcount_t dma_refcnt;
|
|
|
|
@@ -1437,6 +1592,19 @@ static inline u32 mtk_get_ib2_multicast_
|
|
|
|
return MTK_FOE_IB2_MULTICAST;
|
|
|
|
}
|
|
|
|
|
|
|
|
+static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface)
|
|
|
|
+{
|
|
|
|
+ switch (interface) {
|
|
|
|
+ case PHY_INTERFACE_MODE_INTERNAL:
|
|
|
|
+ case PHY_INTERFACE_MODE_USXGMII:
|
|
|
|
+ case PHY_INTERFACE_MODE_10GBASER:
|
|
|
|
+ case PHY_INTERFACE_MODE_5GBASER:
|
|
|
|
+ return true;
|
|
|
|
+ default:
|
|
|
|
+ return false;
|
|
|
|
+ }
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
/* read the hardware status register */
|
|
|
|
void mtk_stats_update_mac(struct mtk_mac *mac);
|
|
|
|
|
|
|
|
@@ -1445,8 +1613,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
|
|
|
|
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
|
|
|
|
|
|
|
|
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
|
|
|
|
+int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
|
|
|
|
int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
|
|
|
|
int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
|
|
|
|
+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id);
|
|
|
|
|
|
|
|
int mtk_eth_offload_init(struct mtk_eth *eth);
|
|
|
|
int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
|
|
|
|
@@ -1456,5 +1626,63 @@ int mtk_flow_offload_cmd(struct mtk_eth
|
|
|
|
void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
|
|
|
|
void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
|
|
|
|
|
|
|
|
+static inline int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
|
|
|
|
+{
|
|
|
|
+ int xgmii_id = mac_id;
|
|
|
|
+
|
|
|
|
+ if (mtk_is_netsys_v3_or_greater(eth)) {
|
|
|
|
+ switch (mac_id) {
|
|
|
|
+ case MTK_GMAC1_ID:
|
|
|
|
+ case MTK_GMAC2_ID:
|
|
|
|
+ xgmii_id = 1;
|
|
|
|
+ break;
|
|
|
|
+ case MTK_GMAC3_ID:
|
|
|
|
+ xgmii_id = 0;
|
|
|
|
+ break;
|
|
|
|
+ default:
|
|
|
|
+ xgmii_id = -1;
|
|
|
|
+ }
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ return MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII) ? 0 : xgmii_id;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static inline int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id)
|
|
|
|
+{
|
|
|
|
+ int mac_id = xgmii_id;
|
|
|
|
+
|
|
|
|
+ if (mtk_is_netsys_v3_or_greater(eth)) {
|
|
|
|
+ switch (xgmii_id) {
|
|
|
|
+ case 0:
|
|
|
|
+ mac_id = 2;
|
|
|
|
+ break;
|
|
|
|
+ case 1:
|
|
|
|
+ mac_id = 1;
|
|
|
|
+ break;
|
|
|
|
+ default:
|
|
|
|
+ mac_id = -1;
|
|
|
|
+ }
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ return mac_id;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII
|
|
|
|
+struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id);
|
|
|
|
+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id);
|
|
|
|
+int mtk_usxgmii_init(struct mtk_eth *eth);
|
|
|
|
+#else
|
|
|
|
+static inline struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id)
|
|
|
|
+{
|
|
|
|
+ return NULL;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id)
|
|
|
|
+{
|
|
|
|
+ return NULL;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; }
|
|
|
|
+#endif /* NET_MEDIATEK_SOC_USXGMII */
|
|
|
|
|
|
|
|
#endif /* MTK_ETH_H */
|
|
|
|
--- /dev/null
|
|
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c
|
|
|
|
@@ -0,0 +1,690 @@
|
|
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
|
|
+/*
|
|
|
|
+ * Copyright (c) 2023 MediaTek Inc.
|
|
|
|
+ * Author: Henry Yen <henry.yen@mediatek.com>
|
|
|
|
+ * Daniel Golle <daniel@makrotopia.org>
|
|
|
|
+ */
|
|
|
|
+
|
|
|
|
+#include <linux/mfd/syscon.h>
|
|
|
|
+#include <linux/of.h>
|
|
|
|
+#include <linux/regmap.h>
|
|
|
|
+#include "mtk_eth_soc.h"
|
|
|
|
+
|
|
|
|
+static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
|
|
|
|
+{
|
|
|
|
+ return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int mtk_xfi_pextp_init(struct mtk_eth *eth)
|
|
|
|
+{
|
|
|
|
+ struct device *dev = eth->dev;
|
|
|
|
+ struct device_node *r = dev->of_node;
|
|
|
|
+ struct device_node *np;
|
|
|
|
+ int i;
|
|
|
|
+
|
|
|
|
+ for (i = 0; i < MTK_MAX_DEVS; i++) {
|
|
|
|
+ np = of_parse_phandle(r, "mediatek,xfi-pextp", i);
|
|
|
|
+ if (!np)
|
|
|
|
+ break;
|
|
|
|
+
|
|
|
|
+ eth->regmap_pextp[i] = syscon_node_to_regmap(np);
|
|
|
|
+ if (IS_ERR(eth->regmap_pextp[i]))
|
|
|
|
+ return PTR_ERR(eth->regmap_pextp[i]);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int mtk_xfi_pll_init(struct mtk_eth *eth)
|
|
|
|
+{
|
|
|
|
+ struct device_node *r = eth->dev->of_node;
|
|
|
|
+ struct device_node *np;
|
|
|
|
+
|
|
|
|
+ np = of_parse_phandle(r, "mediatek,xfi-pll", 0);
|
|
|
|
+ if (!np)
|
|
|
|
+ return -1;
|
|
|
|
+
|
|
|
|
+ eth->usxgmii_pll = syscon_node_to_regmap(np);
|
|
|
|
+ if (IS_ERR(eth->usxgmii_pll))
|
|
|
|
+ return PTR_ERR(eth->usxgmii_pll);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int mtk_toprgu_init(struct mtk_eth *eth)
|
|
|
|
+{
|
|
|
|
+ struct device_node *r = eth->dev->of_node;
|
|
|
|
+ struct device_node *np;
|
|
|
|
+
|
|
|
|
+ np = of_parse_phandle(r, "mediatek,toprgu", 0);
|
|
|
|
+ if (!np)
|
|
|
|
+ return -1;
|
|
|
|
+
|
|
|
|
+ eth->toprgu = syscon_node_to_regmap(np);
|
|
|
|
+ if (IS_ERR(eth->toprgu))
|
|
|
|
+ return PTR_ERR(eth->toprgu);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int mtk_xfi_pll_enable(struct mtk_eth *eth)
|
|
|
|
+{
|
|
|
|
+ u32 val = 0;
|
|
|
|
+
|
|
|
|
+ if (!eth->usxgmii_pll)
|
|
|
|
+ return -EINVAL;
|
|
|
|
+
|
|
|
|
+ /* Add software workaround for USXGMII PLL TCL issue */
|
|
|
|
+ regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
|
|
|
|
+
|
|
|
|
+ regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val);
|
|
|
|
+ val |= RG_XFI_PLL_EN;
|
|
|
|
+ regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void mtk_usxgmii_setup_phya(struct regmap *pextp, phy_interface_t interface, int id)
|
|
|
|
+{
|
|
|
|
+ bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
|
|
|
|
+ interface == PHY_INTERFACE_MODE_USXGMII);
|
|
|
|
+ bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
|
|
|
|
+ bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
|
|
|
|
+
|
|
|
|
+ /* Setup operation mode */
|
|
|
|
+ if (is_10g)
|
|
|
|
+ regmap_write(pextp, 0x9024, 0x00C9071C);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x9024, 0x00D9071C);
|
|
|
|
+
|
|
|
|
+ if (is_5g)
|
|
|
|
+ regmap_write(pextp, 0x2020, 0xAAA5A5AA);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x2020, 0xAA8585AA);
|
|
|
|
+
|
|
|
|
+ if (is_2p5g || is_5g || is_10g) {
|
|
|
|
+ regmap_write(pextp, 0x2030, 0x0C020707);
|
|
|
|
+ regmap_write(pextp, 0x2034, 0x0E050F0F);
|
|
|
|
+ regmap_write(pextp, 0x2040, 0x00140032);
|
|
|
|
+ } else {
|
|
|
|
+ regmap_write(pextp, 0x2030, 0x0C020207);
|
|
|
|
+ regmap_write(pextp, 0x2034, 0x0E05050F);
|
|
|
|
+ regmap_write(pextp, 0x2040, 0x00200032);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (is_2p5g || is_10g)
|
|
|
|
+ regmap_write(pextp, 0x50F0, 0x00C014AA);
|
|
|
|
+ else if (is_5g)
|
|
|
|
+ regmap_write(pextp, 0x50F0, 0x00C018AA);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x50F0, 0x00C014BA);
|
|
|
|
+
|
|
|
|
+ if (is_5g) {
|
|
|
|
+ regmap_write(pextp, 0x50E0, 0x3777812B);
|
|
|
|
+ regmap_write(pextp, 0x506C, 0x005C9CFF);
|
|
|
|
+ regmap_write(pextp, 0x5070, 0x9DFAFAFA);
|
|
|
|
+ regmap_write(pextp, 0x5074, 0x273F3F3F);
|
|
|
|
+ regmap_write(pextp, 0x5078, 0xA8883868);
|
|
|
|
+ regmap_write(pextp, 0x507C, 0x14661466);
|
|
|
|
+ } else {
|
|
|
|
+ regmap_write(pextp, 0x50E0, 0x3777C12B);
|
|
|
|
+ regmap_write(pextp, 0x506C, 0x005F9CFF);
|
|
|
|
+ regmap_write(pextp, 0x5070, 0x9D9DFAFA);
|
|
|
|
+ regmap_write(pextp, 0x5074, 0x27273F3F);
|
|
|
|
+ regmap_write(pextp, 0x5078, 0xA7883C68);
|
|
|
|
+ regmap_write(pextp, 0x507C, 0x11661166);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (is_2p5g || is_10g) {
|
|
|
|
+ regmap_write(pextp, 0x5080, 0x0E000AAF);
|
|
|
|
+ regmap_write(pextp, 0x5084, 0x08080D0D);
|
|
|
|
+ regmap_write(pextp, 0x5088, 0x02030909);
|
|
|
|
+ } else if (is_5g) {
|
|
|
|
+ regmap_write(pextp, 0x5080, 0x0E001ABF);
|
|
|
|
+ regmap_write(pextp, 0x5084, 0x080B0D0D);
|
|
|
|
+ regmap_write(pextp, 0x5088, 0x02050909);
|
|
|
|
+ } else {
|
|
|
|
+ regmap_write(pextp, 0x5080, 0x0E000EAF);
|
|
|
|
+ regmap_write(pextp, 0x5084, 0x08080E0D);
|
|
|
|
+ regmap_write(pextp, 0x5088, 0x02030B09);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (is_5g) {
|
|
|
|
+ regmap_write(pextp, 0x50E4, 0x0C000000);
|
|
|
|
+ regmap_write(pextp, 0x50E8, 0x04000000);
|
|
|
|
+ } else {
|
|
|
|
+ regmap_write(pextp, 0x50E4, 0x0C0C0000);
|
|
|
|
+ regmap_write(pextp, 0x50E8, 0x04040000);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (is_2p5g || mtk_interface_mode_is_xgmii(interface))
|
|
|
|
+ regmap_write(pextp, 0x50EC, 0x0F0F0C06);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x50EC, 0x0F0F0606);
|
|
|
|
+
|
|
|
|
+ if (is_5g) {
|
|
|
|
+ regmap_write(pextp, 0x50A8, 0x50808C8C);
|
|
|
|
+ regmap_write(pextp, 0x6004, 0x18000000);
|
|
|
|
+ } else {
|
|
|
|
+ regmap_write(pextp, 0x50A8, 0x506E8C8C);
|
|
|
|
+ regmap_write(pextp, 0x6004, 0x18190000);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (is_10g)
|
|
|
|
+ regmap_write(pextp, 0x00F8, 0x01423342);
|
|
|
|
+ else if (is_5g)
|
|
|
|
+ regmap_write(pextp, 0x00F8, 0x00A132A1);
|
|
|
|
+ else if (is_2p5g)
|
|
|
|
+ regmap_write(pextp, 0x00F8, 0x009C329C);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x00F8, 0x00FA32FA);
|
|
|
|
+
|
|
|
|
+ /* Force SGDT_OUT off and select PCS */
|
|
|
|
+ if (mtk_interface_mode_is_xgmii(interface))
|
|
|
|
+ regmap_write(pextp, 0x00F4, 0x80201F20);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x00F4, 0x80201F21);
|
|
|
|
+
|
|
|
|
+ /* Force GLB_CKDET_OUT */
|
|
|
|
+ regmap_write(pextp, 0x0030, 0x00050C00);
|
|
|
|
+
|
|
|
|
+ /* Force AEQ on */
|
|
|
|
+ regmap_write(pextp, 0x0070, 0x02002800);
|
|
|
|
+ ndelay(1020);
|
|
|
|
+
|
|
|
|
+ /* Setup DA default value */
|
|
|
|
+ regmap_write(pextp, 0x30B0, 0x00000020);
|
|
|
|
+ regmap_write(pextp, 0x3028, 0x00008A01);
|
|
|
|
+ regmap_write(pextp, 0x302C, 0x0000A884);
|
|
|
|
+ regmap_write(pextp, 0x3024, 0x00083002);
|
|
|
|
+ if (mtk_interface_mode_is_xgmii(interface)) {
|
|
|
|
+ regmap_write(pextp, 0x3010, 0x00022220);
|
|
|
|
+ regmap_write(pextp, 0x5064, 0x0F020A01);
|
|
|
|
+ regmap_write(pextp, 0x50B4, 0x06100600);
|
|
|
|
+ if (interface == PHY_INTERFACE_MODE_USXGMII)
|
|
|
|
+ regmap_write(pextp, 0x3048, 0x40704000);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x3048, 0x47684100);
|
|
|
|
+ } else {
|
|
|
|
+ regmap_write(pextp, 0x3010, 0x00011110);
|
|
|
|
+ regmap_write(pextp, 0x3048, 0x40704000);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (!mtk_interface_mode_is_xgmii(interface) && !is_2p5g)
|
|
|
|
+ regmap_write(pextp, 0x3064, 0x0000C000);
|
|
|
|
+
|
|
|
|
+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
|
|
|
|
+ regmap_write(pextp, 0x3050, 0xA8000000);
|
|
|
|
+ regmap_write(pextp, 0x3054, 0x000000AA);
|
|
|
|
+ } else if (mtk_interface_mode_is_xgmii(interface)) {
|
|
|
|
+ regmap_write(pextp, 0x3050, 0x00000000);
|
|
|
|
+ regmap_write(pextp, 0x3054, 0x00000000);
|
|
|
|
+ } else {
|
|
|
|
+ regmap_write(pextp, 0x3050, 0xA8000000);
|
|
|
|
+ regmap_write(pextp, 0x3054, 0x000000AA);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (mtk_interface_mode_is_xgmii(interface))
|
|
|
|
+ regmap_write(pextp, 0x306C, 0x00000F00);
|
|
|
|
+ else if (is_2p5g)
|
|
|
|
+ regmap_write(pextp, 0x306C, 0x22000F00);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x306C, 0x20200F00);
|
|
|
|
+
|
|
|
|
+ if (interface == PHY_INTERFACE_MODE_10GBASER && id == 0)
|
|
|
|
+ regmap_write(pextp, 0xA008, 0x0007B400);
|
|
|
|
+
|
|
|
|
+ if (mtk_interface_mode_is_xgmii(interface))
|
|
|
|
+ regmap_write(pextp, 0xA060, 0x00040000);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0xA060, 0x00050000);
|
|
|
|
+
|
|
|
|
+ if (is_10g)
|
|
|
|
+ regmap_write(pextp, 0x90D0, 0x00000001);
|
|
|
|
+ else if (is_5g)
|
|
|
|
+ regmap_write(pextp, 0x90D0, 0x00000003);
|
|
|
|
+ else if (is_2p5g)
|
|
|
|
+ regmap_write(pextp, 0x90D0, 0x00000005);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x90D0, 0x00000007);
|
|
|
|
+
|
|
|
|
+ /* Release reset */
|
|
|
|
+ regmap_write(pextp, 0x0070, 0x0200E800);
|
|
|
|
+ usleep_range(150, 500);
|
|
|
|
+
|
|
|
|
+ /* Switch to P0 */
|
|
|
|
+ regmap_write(pextp, 0x0070, 0x0200C111);
|
|
|
|
+ ndelay(1020);
|
|
|
|
+ regmap_write(pextp, 0x0070, 0x0200C101);
|
|
|
|
+ usleep_range(15, 50);
|
|
|
|
+
|
|
|
|
+ if (mtk_interface_mode_is_xgmii(interface)) {
|
|
|
|
+ /* Switch to Gen3 */
|
|
|
|
+ regmap_write(pextp, 0x0070, 0x0202C111);
|
|
|
|
+ } else {
|
|
|
|
+ /* Switch to Gen2 */
|
|
|
|
+ regmap_write(pextp, 0x0070, 0x0201C111);
|
|
|
|
+ }
|
|
|
|
+ ndelay(1020);
|
|
|
|
+ if (mtk_interface_mode_is_xgmii(interface))
|
|
|
|
+ regmap_write(pextp, 0x0070, 0x0202C101);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x0070, 0x0201C101);
|
|
|
|
+ usleep_range(100, 500);
|
|
|
|
+ regmap_write(pextp, 0x30B0, 0x00000030);
|
|
|
|
+ if (mtk_interface_mode_is_xgmii(interface))
|
|
|
|
+ regmap_write(pextp, 0x00F4, 0x80201F00);
|
|
|
|
+ else
|
|
|
|
+ regmap_write(pextp, 0x00F4, 0x80201F01);
|
|
|
|
+
|
|
|
|
+ regmap_write(pextp, 0x3040, 0x30000000);
|
|
|
|
+ usleep_range(400, 1000);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void mtk_usxgmii_reset(struct mtk_eth *eth, int id)
|
|
|
|
+{
|
|
|
|
+ u32 toggle, val;
|
|
|
|
+
|
|
|
|
+ if (id >= MTK_MAX_DEVS || !eth->toprgu)
|
|
|
|
+ return;
|
|
|
|
+
|
|
|
|
+ switch (id) {
|
|
|
|
+ case 0:
|
|
|
|
+ toggle = SWSYSRST_XFI_PEXPT0_GRST | SWSYSRST_XFI0_GRST |
|
|
|
|
+ SWSYSRST_SGMII0_GRST;
|
|
|
|
+ break;
|
|
|
|
+ case 1:
|
|
|
|
+ toggle = SWSYSRST_XFI_PEXPT1_GRST | SWSYSRST_XFI1_GRST |
|
|
|
|
+ SWSYSRST_SGMII1_GRST;
|
|
|
|
+ break;
|
|
|
|
+ default:
|
|
|
|
+ return;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ /* Enable software reset */
|
|
|
|
+ regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
|
|
|
|
+
|
|
|
|
+ /* Assert USXGMII reset */
|
|
|
|
+ regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST,
|
|
|
|
+ FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | toggle);
|
|
|
|
+
|
|
|
|
+ usleep_range(100, 500);
|
|
|
|
+
|
|
|
|
+ /* De-assert USXGMII reset */
|
|
|
|
+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
|
|
|
|
+ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
|
|
|
|
+ val &= ~toggle;
|
|
|
|
+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
|
|
|
|
+
|
|
|
|
+ /* Disable software reset */
|
|
|
|
+ regmap_clear_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
|
|
|
|
+
|
|
|
|
+ mdelay(10);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+/* As the USXGMII PHYA is shared with the 1000Base-X/2500Base-X/Cisco SGMII unit
|
|
|
|
+ * the psc-mtk-lynxi instance needs to be wrapped, so that calls to .pcs_config
|
|
|
|
+ * also trigger an initial reset and subsequent configuration of the PHYA.
|
|
|
|
+ */
|
|
|
|
+struct mtk_sgmii_wrapper_pcs {
|
|
|
|
+ struct mtk_eth *eth;
|
|
|
|
+ struct phylink_pcs *wrapped_pcs;
|
|
|
|
+ u8 id;
|
|
|
|
+ struct phylink_pcs pcs;
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static int mtk_sgmii_wrapped_pcs_config(struct phylink_pcs *pcs,
|
|
|
|
+ unsigned int mode,
|
|
|
|
+ phy_interface_t interface,
|
|
|
|
+ const unsigned long *advertising,
|
|
|
|
+ bool permit_pause_to_mac)
|
|
|
|
+{
|
|
|
|
+ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
|
|
|
|
+ bool full_reconf;
|
|
|
|
+ int ret;
|
|
|
|
+
|
|
|
|
+ full_reconf = interface != wp->eth->usxgmii_pcs[wp->id]->interface;
|
|
|
|
+ if (full_reconf) {
|
|
|
|
+ mtk_xfi_pll_enable(wp->eth);
|
|
|
|
+ mtk_usxgmii_reset(wp->eth, wp->id);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ ret = wp->wrapped_pcs->ops->pcs_config(wp->wrapped_pcs, mode, interface,
|
|
|
|
+ advertising, permit_pause_to_mac);
|
|
|
|
+
|
|
|
|
+ if (full_reconf)
|
|
|
|
+ mtk_usxgmii_setup_phya(wp->eth->regmap_pextp[wp->id], interface, wp->id);
|
|
|
|
+
|
|
|
|
+ wp->eth->usxgmii_pcs[wp->id]->interface = interface;
|
|
|
|
+
|
|
|
|
+ return ret;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void mtk_sgmii_wrapped_pcs_get_state(struct phylink_pcs *pcs,
|
|
|
|
+ struct phylink_link_state *state)
|
|
|
|
+{
|
|
|
|
+ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
|
|
|
|
+
|
|
|
|
+ return wp->wrapped_pcs->ops->pcs_get_state(wp->wrapped_pcs, state);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void mtk_sgmii_wrapped_pcs_an_restart(struct phylink_pcs *pcs)
|
|
|
|
+{
|
|
|
|
+ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
|
|
|
|
+
|
|
|
|
+ wp->wrapped_pcs->ops->pcs_an_restart(wp->wrapped_pcs);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void mtk_sgmii_wrapped_pcs_link_up(struct phylink_pcs *pcs,
|
|
|
|
+ unsigned int mode,
|
|
|
|
+ phy_interface_t interface, int speed,
|
|
|
|
+ int duplex)
|
|
|
|
+{
|
|
|
|
+ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
|
|
|
|
+
|
|
|
|
+ wp->wrapped_pcs->ops->pcs_link_up(wp->wrapped_pcs, mode, interface, speed, duplex);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void mtk_sgmii_wrapped_pcs_disable(struct phylink_pcs *pcs)
|
|
|
|
+{
|
|
|
|
+ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
|
|
|
|
+
|
|
|
|
+ wp->wrapped_pcs->ops->pcs_disable(wp->wrapped_pcs);
|
|
|
|
+
|
|
|
|
+ wp->eth->usxgmii_pcs[wp->id]->interface = PHY_INTERFACE_MODE_NA;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static const struct phylink_pcs_ops mtk_sgmii_wrapped_pcs_ops = {
|
|
|
|
+ .pcs_get_state = mtk_sgmii_wrapped_pcs_get_state,
|
|
|
|
+ .pcs_config = mtk_sgmii_wrapped_pcs_config,
|
|
|
|
+ .pcs_an_restart = mtk_sgmii_wrapped_pcs_an_restart,
|
|
|
|
+ .pcs_link_up = mtk_sgmii_wrapped_pcs_link_up,
|
|
|
|
+ .pcs_disable = mtk_sgmii_wrapped_pcs_disable,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static int mtk_sgmii_wrapper_init(struct mtk_eth *eth)
|
|
|
|
+{
|
|
|
|
+ struct mtk_sgmii_wrapper_pcs *wp;
|
|
|
|
+ int i;
|
|
|
|
+
|
|
|
|
+ for (i = 0; i < MTK_MAX_DEVS; i++) {
|
|
|
|
+ if (!eth->sgmii_pcs[i])
|
|
|
|
+ continue;
|
|
|
|
+
|
|
|
|
+ if (!eth->usxgmii_pcs[i])
|
|
|
|
+ continue;
|
|
|
|
+
|
|
|
|
+ /* Make sure all PCS ops are supported by wrapped PCS */
|
|
|
|
+ if (!eth->sgmii_pcs[i]->ops->pcs_get_state ||
|
|
|
|
+ !eth->sgmii_pcs[i]->ops->pcs_config ||
|
|
|
|
+ !eth->sgmii_pcs[i]->ops->pcs_an_restart ||
|
|
|
|
+ !eth->sgmii_pcs[i]->ops->pcs_link_up ||
|
|
|
|
+ !eth->sgmii_pcs[i]->ops->pcs_disable)
|
|
|
|
+ return -EOPNOTSUPP;
|
|
|
|
+
|
|
|
|
+ wp = devm_kzalloc(eth->dev, sizeof(*wp), GFP_KERNEL);
|
|
|
|
+ if (!wp)
|
|
|
|
+ return -ENOMEM;
|
|
|
|
+
|
|
|
|
+ wp->wrapped_pcs = eth->sgmii_pcs[i];
|
|
|
|
+ wp->id = i;
|
|
|
|
+ wp->pcs.poll = true;
|
|
|
|
+ wp->pcs.ops = &mtk_sgmii_wrapped_pcs_ops;
|
|
|
|
+ wp->eth = eth;
|
|
|
|
+
|
|
|
|
+ eth->usxgmii_pcs[i]->wrapped_sgmii_pcs = &wp->pcs;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int mac_id)
|
|
|
|
+{
|
|
|
|
+ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
|
|
|
|
+
|
|
|
|
+ if (!eth->usxgmii_pcs[xgmii_id])
|
|
|
|
+ return NULL;
|
|
|
|
+
|
|
|
|
+ return eth->usxgmii_pcs[xgmii_id]->wrapped_sgmii_pcs;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
|
|
|
|
+ phy_interface_t interface,
|
|
|
|
+ const unsigned long *advertising,
|
|
|
|
+ bool permit_pause_to_mac)
|
|
|
|
+{
|
|
|
|
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
|
|
|
|
+ struct mtk_eth *eth = mpcs->eth;
|
|
|
|
+ struct regmap *pextp = eth->regmap_pextp[mpcs->id];
|
|
|
|
+ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
|
|
|
|
+ bool mode_changed = false;
|
|
|
|
+
|
|
|
|
+ if (!pextp)
|
|
|
|
+ return -ENODEV;
|
|
|
|
+
|
|
|
|
+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
|
|
|
|
+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
|
|
|
|
+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
|
|
|
|
+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
|
|
|
|
+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
|
|
|
|
+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
|
|
|
|
+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
|
|
|
|
+ } else if (interface == PHY_INTERFACE_MODE_10GBASER) {
|
|
|
|
+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
|
|
|
|
+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
|
|
|
|
+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
|
|
|
|
+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
|
|
|
|
+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
|
|
|
|
+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
|
|
|
|
+ adapt_mode = USXGMII_RATE_UPDATE_MODE;
|
|
|
|
+ } else if (interface == PHY_INTERFACE_MODE_5GBASER) {
|
|
|
|
+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
|
|
|
|
+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
|
|
|
|
+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
|
|
|
|
+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
|
|
|
|
+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) |
|
|
|
|
+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G);
|
|
|
|
+ adapt_mode = USXGMII_RATE_UPDATE_MODE;
|
|
|
|
+ } else {
|
|
|
|
+ return -EINVAL;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
|
|
|
|
+
|
|
|
|
+ if (mpcs->interface != interface) {
|
|
|
|
+ mpcs->interface = interface;
|
|
|
|
+ mode_changed = true;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ mtk_xfi_pll_enable(eth);
|
|
|
|
+ mtk_usxgmii_reset(eth, mpcs->id);
|
|
|
|
+
|
|
|
|
+ /* Setup USXGMII AN ctrl */
|
|
|
|
+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0,
|
|
|
|
+ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
|
|
|
|
+ an_ctrl);
|
|
|
|
+
|
|
|
|
+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2,
|
|
|
|
+ USXGMII_LINK_TIMER_IDLE_DETECT |
|
|
|
|
+ USXGMII_LINK_TIMER_COMP_ACK_DETECT |
|
|
|
|
+ USXGMII_LINK_TIMER_AN_RESTART,
|
|
|
|
+ link_timer);
|
|
|
|
+
|
|
|
|
+ mpcs->mode = mode;
|
|
|
|
+
|
|
|
|
+ /* Gated MAC CK */
|
|
|
|
+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
|
|
|
|
+ USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
|
|
|
|
+
|
|
|
|
+ /* Enable interface force mode */
|
|
|
|
+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
|
|
|
|
+ USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
|
|
|
|
+
|
|
|
|
+ /* Setup USXGMII adapt mode */
|
|
|
|
+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
|
|
|
|
+ USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
|
|
|
|
+ adapt_mode);
|
|
|
|
+
|
|
|
|
+ /* Setup USXGMII speed */
|
|
|
|
+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
|
|
|
|
+ USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
|
|
|
|
+ xfi_mode);
|
|
|
|
+
|
|
|
|
+ usleep_range(1, 10);
|
|
|
|
+
|
|
|
|
+ /* Un-gated MAC CK */
|
|
|
|
+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
|
|
|
|
+ USXGMII_MAC_CK_GATED, 0);
|
|
|
|
+
|
|
|
|
+ usleep_range(1, 10);
|
|
|
|
+
|
|
|
|
+ /* Disable interface force mode for the AN mode */
|
|
|
|
+ if (an_ctrl & USXGMII_AN_ENABLE)
|
|
|
|
+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
|
|
|
|
+ USXGMII_IF_FORCE_EN, 0);
|
|
|
|
+
|
|
|
|
+ /* Setup USXGMIISYS with the determined property */
|
|
|
|
+ mtk_usxgmii_setup_phya(pextp, interface, mpcs->id);
|
|
|
|
+
|
|
|
|
+ return mode_changed;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
|
|
|
|
+ struct phylink_link_state *state)
|
|
|
|
+{
|
|
|
|
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
|
|
|
|
+ struct mtk_eth *eth = mpcs->eth;
|
|
|
|
+ struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)];
|
|
|
|
+ u32 val = 0;
|
|
|
|
+
|
|
|
|
+ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
|
|
|
|
+ if (FIELD_GET(USXGMII_AN_ENABLE, val)) {
|
|
|
|
+ /* Refresh LPA by inverting LPA_LATCH */
|
|
|
|
+ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
|
|
|
|
+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0,
|
|
|
|
+ USXGMII_LPA_LATCH,
|
|
|
|
+ !(val & USXGMII_LPA_LATCH));
|
|
|
|
+
|
|
|
|
+ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
|
|
|
|
+
|
|
|
|
+ phylink_decode_usxgmii_word(state, FIELD_GET(USXGMII_PCS_AN_WORD,
|
|
|
|
+ val));
|
|
|
|
+
|
|
|
|
+ state->interface = mpcs->interface;
|
|
|
|
+ } else {
|
|
|
|
+ val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
|
|
|
|
+
|
|
|
|
+ if (mac->id == MTK_GMAC2_ID)
|
|
|
|
+ val >>= 16;
|
|
|
|
+
|
|
|
|
+ switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) {
|
|
|
|
+ case 0:
|
|
|
|
+ state->speed = SPEED_10000;
|
|
|
|
+ break;
|
|
|
|
+ case 1:
|
|
|
|
+ state->speed = SPEED_5000;
|
|
|
|
+ break;
|
|
|
|
+ case 2:
|
|
|
|
+ state->speed = SPEED_2500;
|
|
|
|
+ break;
|
|
|
|
+ case 3:
|
|
|
|
+ state->speed = SPEED_1000;
|
|
|
|
+ break;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ state->interface = mpcs->interface;
|
|
|
|
+ state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val);
|
|
|
|
+ state->duplex = DUPLEX_FULL;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ /* Continuously repeat re-configuration sequence until link comes up */
|
|
|
|
+ if (state->link == 0)
|
|
|
|
+ mtk_usxgmii_pcs_config(pcs, mpcs->mode,
|
|
|
|
+ state->interface, NULL, false);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
|
|
|
|
+{
|
|
|
|
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
|
|
|
|
+ unsigned int val = 0;
|
|
|
|
+
|
|
|
|
+ if (!mpcs->regmap)
|
|
|
|
+ return;
|
|
|
|
+
|
|
|
|
+ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
|
|
|
|
+ val |= USXGMII_AN_RESTART;
|
|
|
|
+ regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
|
|
|
|
+ phy_interface_t interface,
|
|
|
|
+ int speed, int duplex)
|
|
|
|
+{
|
|
|
|
+ /* Reconfiguring USXGMII to ensure the quality of the RX signal
|
|
|
|
+ * after the line side link up.
|
|
|
|
+ */
|
|
|
|
+ mtk_usxgmii_pcs_config(pcs, mode,
|
|
|
|
+ interface, NULL, false);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
|
|
|
|
+ .pcs_config = mtk_usxgmii_pcs_config,
|
|
|
|
+ .pcs_get_state = mtk_usxgmii_pcs_get_state,
|
|
|
|
+ .pcs_an_restart = mtk_usxgmii_pcs_restart_an,
|
|
|
|
+ .pcs_link_up = mtk_usxgmii_pcs_link_up,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+int mtk_usxgmii_init(struct mtk_eth *eth)
|
|
|
|
+{
|
|
|
|
+ struct device_node *r = eth->dev->of_node;
|
|
|
|
+ struct device *dev = eth->dev;
|
|
|
|
+ struct device_node *np;
|
|
|
|
+ int i, ret;
|
|
|
|
+
|
|
|
|
+ for (i = 0; i < MTK_MAX_DEVS; i++) {
|
|
|
|
+ np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
|
|
|
|
+ if (!np)
|
|
|
|
+ break;
|
|
|
|
+
|
|
|
|
+ eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs[i]), GFP_KERNEL);
|
|
|
|
+ if (!eth->usxgmii_pcs[i])
|
|
|
|
+ return -ENOMEM;
|
|
|
|
+
|
|
|
|
+ eth->usxgmii_pcs[i]->id = i;
|
|
|
|
+ eth->usxgmii_pcs[i]->eth = eth;
|
|
|
|
+ eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np);
|
|
|
|
+ if (IS_ERR(eth->usxgmii_pcs[i]->regmap))
|
|
|
|
+ return PTR_ERR(eth->usxgmii_pcs[i]->regmap);
|
|
|
|
+
|
|
|
|
+ eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops;
|
|
|
|
+ eth->usxgmii_pcs[i]->pcs.poll = true;
|
|
|
|
+ eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA;
|
|
|
|
+ eth->usxgmii_pcs[i]->mode = -1;
|
|
|
|
+
|
|
|
|
+ of_node_put(np);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ ret = mtk_xfi_pextp_init(eth);
|
|
|
|
+ if (ret)
|
|
|
|
+ return ret;
|
|
|
|
+
|
|
|
|
+ ret = mtk_xfi_pll_init(eth);
|
|
|
|
+ if (ret)
|
|
|
|
+ return ret;
|
|
|
|
+
|
|
|
|
+ ret = mtk_toprgu_init(eth);
|
|
|
|
+ if (ret)
|
|
|
|
+ return ret;
|
|
|
|
+
|
|
|
|
+ return mtk_sgmii_wrapper_init(eth);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id)
|
|
|
|
+{
|
|
|
|
+ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
|
|
|
|
+
|
|
|
|
+ if (!eth->usxgmii_pcs[xgmii_id]->regmap)
|
|
|
|
+ return NULL;
|
|
|
|
+
|
|
|
|
+ return ð->usxgmii_pcs[xgmii_id]->pcs;
|
|
|
|
+}
|