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61 lines
2.2 KiB
Diff
61 lines
2.2 KiB
Diff
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From 66a7752834382595d26214783ae4698fd1f00bd6 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Thu, 13 May 2021 14:53:44 +0200
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Subject: [PATCH] fix(plat/marvell/a3720/uart): fix UART clock rate value and
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divisor calculation
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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UART parent clock is by default the platform's xtal clock, which is
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25 MHz.
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The value defined in the driver, though, is 25.8048 MHz. This is a hack
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for the suboptimal divisor calculation
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Divisor = UART clock / (16 * baudrate)
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which does not use rounding division, resulting in a suboptimal value
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for divisor if the correct parent clock rate was used.
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Change the code for divisor calculation to
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Divisor = Round(UART clock / (16 * baudrate))
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and change the parent clock rate value to 25 MHz.
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The final UART divisor for default baudrate 115200 is not affected by
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this change.
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(Note that the parent clock rate should not be defined via a macro,
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since the xtal clock can also be 40 MHz. This is outside of the scope of
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this fix, though.)
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
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---
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drivers/marvell/uart/a3700_console.S | 3 ++-
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plat/marvell/armada/a3k/common/include/platform_def.h | 2 +-
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2 files changed, 3 insertions(+), 2 deletions(-)
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--- a/drivers/marvell/uart/a3700_console.S
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+++ b/drivers/marvell/uart/a3700_console.S
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@@ -45,8 +45,9 @@ func console_a3700_core_init
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cbz w2, init_fail
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/* Program the baudrate */
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- /* Divisor = Uart clock / (16 * baudrate) */
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+ /* Divisor = Round(Uartclock / (16 * baudrate)) */
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lsl w2, w2, #4
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+ add w1, w1, w2, lsr #1
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udiv w2, w1, w2
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and w2, w2, #0x3ff
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--- a/plat/marvell/armada/a3k/common/include/platform_def.h
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+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
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@@ -164,7 +164,7 @@
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* PL011 related constants
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*/
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#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
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-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800
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+#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25000000
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#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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