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64 lines
2.8 KiB
Diff
64 lines
2.8 KiB
Diff
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From patchwork Thu Sep 28 12:58:37 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v2,6/7] PCI: aardvark: fix PCIe max read request size setting
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X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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X-Patchwork-Id: 819591
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Message-Id: <20170928125838.11887-7-thomas.petazzoni@free-electrons.com>
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To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
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Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
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Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
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<gregory.clement@free-electrons.com>,
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Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
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Yehuda Yitschak <yehuday@marvell.com>,
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linux-arm-kernel@lists.infradead.org, Antoine Tenart
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<antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
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<miquel.raynal@free-electrons.com>, Evan Wang <xswang@marvell.com>,
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Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 28 Sep 2017 14:58:37 +0200
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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List-Id: <linux-pci.vger.kernel.org>
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From: Evan Wang <xswang@marvell.com>
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There is an obvious typo issue in the definition of the PCIe maximum
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read request size: a bit shift is directly used as a value, while it
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should be used to shift the correct value.
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This is part of fixing bug
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https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
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reported as the user to be important to get a Intel 7260 mini-PCIe
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WiFi card working.
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Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Evan Wang <xswang@marvell.com>
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Reviewed-by: Victor Gu <xigu@marvell.com>
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Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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[Thomas: tweak commit log.]
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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drivers/pci/host/pci-aardvark.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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--- a/drivers/pci/host/pci-aardvark.c
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+++ b/drivers/pci/host/pci-aardvark.c
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@@ -33,6 +33,7 @@
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
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#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
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#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
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+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
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#define PCIE_CORE_MPS_UNIT_BYTE 128
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#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
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#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
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@@ -303,7 +304,8 @@ static void advk_pcie_setup_hw(struct ad
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(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
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PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
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PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
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- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
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+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
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+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
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advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
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/* Program PCIe Control 2 to disable strict ordering */
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