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88 lines
3.6 KiB
Diff
88 lines
3.6 KiB
Diff
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From c53200aa7d0670aa21639512880669b94699aaee Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Tue, 15 Dec 2020 16:42:35 +0100
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Subject: [PATCH] drm/vc4: hvs: Align the HVS atomic hooks to the new
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API
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Since the CRTC setup in vc4 is split between the PixelValves/TXP and the
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HVS, only the PV/TXP atomic hooks were updated in the previous commits, but
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it makes sense to update the HVS ones too.
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Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Link: https://patchwork.freedesktop.org/patch/msgid/20201215154243.540115-2-maxime@cerno.tech
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
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drivers/gpu/drm/vc4/vc4_drv.h | 5 ++---
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drivers/gpu/drm/vc4/vc4_hvs.c | 10 +++++-----
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drivers/gpu/drm/vc4/vc4_txp.c | 2 +-
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4 files changed, 9 insertions(+), 10 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -646,7 +646,7 @@ static int vc4_crtc_atomic_check(struct
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struct drm_connector_state *conn_state;
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int ret, i;
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- ret = vc4_hvs_atomic_check(crtc, crtc_state);
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+ ret = vc4_hvs_atomic_check(crtc, state);
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if (ret)
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return ret;
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -924,11 +924,10 @@ void vc4_irq_reset(struct drm_device *de
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extern struct platform_driver vc4_hvs_driver;
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void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
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int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
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-int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
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+int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
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void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
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void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);
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-void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
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- struct drm_atomic_state *state);
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+void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state);
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void vc4_hvs_dump_state(struct drm_device *dev);
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void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
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void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -365,10 +365,10 @@ void vc4_hvs_stop_channel(struct drm_dev
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SCALER_DISPSTATX_EMPTY);
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}
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-int vc4_hvs_atomic_check(struct drm_crtc *crtc,
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- struct drm_crtc_state *state)
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+int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
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{
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- struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
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+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
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+ struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_plane *plane;
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@@ -380,10 +380,10 @@ int vc4_hvs_atomic_check(struct drm_crtc
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/* The pixelvalve can only feed one encoder (and encoders are
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* 1:1 with connectors.)
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*/
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- if (hweight32(state->connector_mask) > 1)
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+ if (hweight32(crtc_state->connector_mask) > 1)
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return -EINVAL;
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- drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
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+ drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state)
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dlist_count += vc4_plane_dlist_size(plane_state);
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dlist_count++; /* Account for SCALER_CTL0_END. */
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--- a/drivers/gpu/drm/vc4/vc4_txp.c
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+++ b/drivers/gpu/drm/vc4/vc4_txp.c
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@@ -393,7 +393,7 @@ static int vc4_txp_atomic_check(struct d
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
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int ret;
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- ret = vc4_hvs_atomic_check(crtc, crtc_state);
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+ ret = vc4_hvs_atomic_check(crtc, state);
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if (ret)
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return ret;
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