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43 lines
1.6 KiB
Diff
43 lines
1.6 KiB
Diff
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From 9f7c0728efb0036f6f197126aa62da40cdf4713a Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Wed, 28 Apr 2021 16:14:21 +0100
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Subject: [PATCH] drm/vc4: Allow DBLCLK modes even if horz timing is
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odd.
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The 2711 pixel valve can't produce odd horizontal timings, and
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checks were added to vc4_hdmi_encoder_atomic_check and
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vc4_hdmi_encoder_mode_valid to filter out/block selection of
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such modes.
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Modes with DRM_MODE_FLAG_DBLCLK double all the horizontal timing
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values before programming them into the PV. The PV values,
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therefore, can not be odd, and so the modes can be supported.
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Amend the filtering appropriately.
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See https://github.com/raspberrypi/linux/issues/4307
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 2 ++
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1 file changed, 2 insertions(+)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -1066,6 +1066,7 @@ static int vc4_hdmi_encoder_atomic_check
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unsigned long long tmds_rate;
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if (vc4_hdmi->variant->unsupported_odd_h_timings &&
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+ !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
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((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
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(mode->hsync_end % 2) || (mode->htotal % 2)))
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return -EINVAL;
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@@ -1110,6 +1111,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_e
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struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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if (vc4_hdmi->variant->unsupported_odd_h_timings &&
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+ !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
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((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
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(mode->hsync_end % 2) || (mode->htotal % 2)))
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return MODE_H_ILLEGAL;
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