mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 17:18:59 +00:00
29 lines
873 B
Diff
29 lines
873 B
Diff
|
From 418603fdce51212d4547aacfe2b4801fc5e61978 Mon Sep 17 00:00:00 2001
|
||
|
From: Emil Renner Berthing <kernel@esmil.dk>
|
||
|
Date: Sat, 20 Nov 2021 21:33:08 +0100
|
||
|
Subject: [PATCH 1015/1024] RISC-V: Add StarFive JH7100 audio reset node
|
||
|
|
||
|
Add device tree node for the audio resets on the StarFive JH7100 RISC-V
|
||
|
SoC.
|
||
|
|
||
|
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
|
||
|
---
|
||
|
arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++
|
||
|
1 file changed, 6 insertions(+)
|
||
|
|
||
|
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
||
|
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
||
|
@@ -168,6 +168,12 @@
|
||
|
#clock-cells = <1>;
|
||
|
};
|
||
|
|
||
|
+ audrst: reset-controller@10490000 {
|
||
|
+ compatible = "starfive,jh7100-audrst";
|
||
|
+ reg = <0x0 0x10490000 0x0 0x10000>;
|
||
|
+ #reset-cells = <1>;
|
||
|
+ };
|
||
|
+
|
||
|
clkgen: clock-controller@11800000 {
|
||
|
compatible = "starfive,jh7100-clkgen";
|
||
|
reg = <0x0 0x11800000 0x0 0x10000>;
|