openwrt/target/linux/starfive/patches-6.6/0075-RISC-V-Added-generic-pmu-events-mapfile.patch

From 3e6ea12dda276c01a756764fcafa315b19860c33 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jo=C3=A3o=20M=C3=A1rio=20Domingos?=
 <joao.mario@tecnico.ulisboa.pt>
Date: Tue, 16 Nov 2021 15:48:11 +0000
Subject: [PATCH 075/116] RISC-V: Added generic pmu-events mapfile
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The pmu-events now supports custom events for RISC-V, plus the cycle,
time and instret events were defined.

Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
---
 .../pmu-events/arch/riscv/riscv-generic.json  | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json

--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
@@ -0,0 +1,20 @@
+[
+  {
+    "PublicDescription": "CPU Cycles",
+    "EventCode": "0x00",
+    "EventName": "riscv_cycles",
+    "BriefDescription": "CPU cycles RISC-V generic counter"
+  },
+  {
+    "PublicDescription": "CPU Time",
+      "EventCode": "0x01",
+      "EventName": "riscv_time",
+      "BriefDescription": "CPU time RISC-V generic counter"
+  },
+  {
+    "PublicDescription": "CPU Instructions",
+      "EventCode": "0x02",
+      "EventName": "riscv_instret",
+      "BriefDescription": "CPU retired instructions RISC-V generic counter"
+  }
+]
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